Discussion:
[PATCH 0/6] x86: further template folding and misc improvements
Jan Beulich
2018-08-02 06:44:01 UTC
Permalink
1: drop "mem" operand type attribute
2: drop NoRex64 from {,v}pmov{s,z}x*
3: improve operand reversal
4: use D attribute also for SIMD templates
5: also allow D on 3-operand insns
6: fold RegEip/RegRip and RegEiz/RegRiz

Jan
Jan Beulich
2018-08-02 06:48:16 UTC
Permalink
No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.

gas/
2018-08-02 Jan Beulich <***@suse.com>

* config/tc-i386.c (Operand_Mem): Define.
(operand_size_match): Use it.
(check_VecOperands): Likewise.
(i386_att_operand): Likewise.
(swap_2_operands): Also swap flags fields.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.

opcodes/
2018-08-02 Jan Beulich <***@suse.com>

* i386-gen.c (operand_types): Remove Mem field.
* i386-opc.h (union i386_operand_type): Remove mem field.
* i386-init.h, i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -875,7 +875,7 @@ i386_intel_operand (char *operand_string
i.mem_operands = 0;
i.disp_operands = 0;
i.imm_operands = 2;
- i.types[0].bitfield.mem = 0;
+ i.flags[0] &= ~Operand_Mem;
i.types[0].bitfield.disp16 = 0;
i.types[0].bitfield.disp32 = 0;
i.types[0].bitfield.disp32s = 0;
@@ -1009,7 +1009,7 @@ i386_intel_operand (char *operand_string
if (!i386_index_check (operand_string))
return 0;

- i.types[this_operand].bitfield.mem = 1;
+ i.flags[this_operand] |= Operand_Mem;
if (i.mem_operands == 0)
i.memop1_string = xstrdup (operand_string);
++i.mem_operands;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -309,6 +309,7 @@ struct _i386_insn
/* Flags for operands. */
unsigned int flags[MAX_OPERANDS];
#define Operand_PCrel 1
+#define Operand_Mem 2

/* Relocation type for operand */
enum bfd_reloc_code_real reloc[MAX_OPERANDS];
@@ -2010,7 +2011,7 @@ operand_size_match (const insn_template
break;
}

- if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
+ if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
{
match = 0;
break;
@@ -2035,8 +2036,7 @@ mismatch:
&& !match_operand_size (t, j, !j))
goto mismatch;

- if (i.types[!j].bitfield.mem
- && !match_mem_size (t, j, !j))
+ if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
goto mismatch;
}

@@ -4753,14 +4753,21 @@ swap_2_operands (int xchg1, int xchg2)
{
union i386_op temp_op;
i386_operand_type temp_type;
+ unsigned int temp_flags;
enum bfd_reloc_code_real temp_reloc;

temp_type = i.types[xchg2];
i.types[xchg2] = i.types[xchg1];
i.types[xchg1] = temp_type;
+
+ temp_flags = i.flags[xchg2];
+ i.flags[xchg2] = i.flags[xchg1];
+ i.flags[xchg1] = temp_flags;
+
temp_op = i.op[xchg2];
i.op[xchg2] = i.op[xchg1];
i.op[xchg1] = temp_op;
+
temp_reloc = i.reloc[xchg2];
i.reloc[xchg2] = i.reloc[xchg1];
i.reloc[xchg1] = temp_reloc;
@@ -5180,7 +5187,7 @@ check_VecOperands (const insn_template *
and its broadcast bytes match the memory operand. */
op = i.broadcast->operand;
if (!t->opcode_modifier.broadcast
- || !i.types[op].bitfield.mem
+ || !(i.flags[op] & Operand_Mem)
|| (!i.types[op].bitfield.unspecified
&& !match_broadcast_size (t, op)))
{
@@ -5276,7 +5283,7 @@ check_VecOperands (const insn_template *
{
/* Find memory operand. */
for (op = 0; op < i.operands; op++)
- if (i.types[op].bitfield.mem)
+ if (i.flags[op] & Operand_Mem)
break;
gas_assert (op < i.operands);
if (op == i.operands - 1)
@@ -9814,7 +9821,7 @@ i386_att_operand (char *operand_string)

if (i386_index_check (operand_string) == 0)
return 0;
- i.types[this_operand].bitfield.mem = 1;
+ i.flags[this_operand] |= Operand_Mem;
if (i.mem_operands == 0)
i.memop1_string = xstrdup (operand_string);
i.mem_operands++;
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -685,7 +685,6 @@ static bitfield operand_types[] =
BITFIELD (JumpAbsolute),
BITFIELD (EsSeg),
BITFIELD (RegMem),
- BITFIELD (Mem),
BITFIELD (Byte),
BITFIELD (Word),
BITFIELD (Dword),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -819,7 +819,6 @@ typedef union i386_operand_type
unsigned int jumpabsolute:1;
unsigned int esseg:1;
unsigned int regmem:1;
- unsigned int mem:1;
unsigned int byte:1;
unsigned int word:1;
unsigned int dword:1;
H.J. Lu
2018-08-02 12:20:21 UTC
Permalink
Post by Jan Beulich
No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.
gas/
* config/tc-i386.c (Operand_Mem): Define.
(operand_size_match): Use it.
(check_VecOperands): Likewise.
(i386_att_operand): Likewise.
(swap_2_operands): Also swap flags fields.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
opcodes/
* i386-gen.c (operand_types): Remove Mem field.
* i386-opc.h (union i386_operand_type): Remove mem field.
* i386-init.h, i386-tbl.h: Re-generate.
OK.

Thanks.
--
H.J.
Jan Beulich
2018-08-02 06:49:02 UTC
Permalink
They're pointless with IgnoreSize also specified, and even more so when
no Qword operand exists.

opcodes/
2018-08-02 Jan Beulich <***@suse.com>

* i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
vpmovzxdq, vpmovzxwd): Remove NoRex64.
* i386-tbl.h: Re-generate.

--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1707,30 +1707,30 @@ pminud, 2, 0x663b, None, 1, CpuAVX, Modr
pminud, 2, 0x660f383b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pminuw, 2, 0x663a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pminuw, 2, 0x660f383a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovsxbw, 2, 0x660f3820, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovsxbw, 2, 0x660f3820, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovsxbd, 2, 0x660f3821, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovsxbq, 2, 0x660f3822, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovsxwd, 2, 0x660f3823, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovsxwd, 2, 0x660f3823, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovsxwq, 2, 0x6624, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovsxwq, 2, 0x660f3824, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovsxdq, 2, 0x660f3825, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovzxbw, 2, 0x660f3830, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovsxdq, 2, 0x660f3825, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovzxbw, 2, 0x660f3830, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovzxbd, 2, 0x6631, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovzxbd, 2, 0x660f3831, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovzxbq, 2, 0x6632, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovzxbq, 2, 0x660f3832, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovzxwd, 2, 0x660f3833, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovzxwd, 2, 0x660f3833, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmovzxwq, 2, 0x660f3834, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-pmovzxdq, 2, 0x660f3835, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+pmovzxdq, 2, 0x660f3835, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
pmuldq, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmuldq, 2, 0x660f3828, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pmulld, 2, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -2175,15 +2175,15 @@ vpminuw, 3, 0x663a, None, 1, CpuAVX, Mod
vpmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
vpmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovsxwq, 2, 0x6624, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovzxbd, 2, 0x6631, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovzxbq, 2, 0x6632, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmuldq, 3, 0x6628, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vpmulhrsw, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -2326,15 +2326,15 @@ vpminuw, 3, 0x663a, None, 1, CpuAVX2, Mo
vpmovmskb, 2, 0x66d7, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 }
vpmovsxbd, 2, 0x6621, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovsxbq, 2, 0x6622, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovsxbw, 2, 0x6620, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovsxdq, 2, 0x6625, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovsxwd, 2, 0x6623, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovsxbw, 2, 0x6620, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovsxdq, 2, 0x6625, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovsxwd, 2, 0x6623, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovsxwq, 2, 0x6624, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovzxbd, 2, 0x6631, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovzxbq, 2, 0x6632, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxbw, 2, 0x6630, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxdq, 2, 0x6635, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxwd, 2, 0x6633, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovzxbw, 2, 0x6630, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovzxdq, 2, 0x6635, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovzxwd, 2, 0x6633, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovzxwq, 2, 0x6634, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
vpmuldq, 3, 0x6628, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
vpmulhrsw, 3, 0x660b, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
H.J. Lu
2018-08-02 12:20:45 UTC
Permalink
Post by Jan Beulich
They're pointless with IgnoreSize also specified, and even more so when
no Qword operand exists.
opcodes/
* i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
vpmovzxdq, vpmovzxwd): Remove NoRex64.
* i386-tbl.h: Re-generate.
OK. Thanks.
--
H.J.
Jan Beulich
2018-08-02 06:49:57 UTC
Permalink
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.

The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.

gas/
2018-08-02 Jan Beulich <***@suse.com>

* config/tc-i386.c (dir_encoding_swap): New enumerator.
(parse_insn): Use it.
(match_template): Re-write reversal check.
* testsuite/gas/i386/opts.s: Add mov, FPU, and vmov* tests.
* testsuite/gas/i386/x86-64-opts.s: Likewise, plus bndmov.
* testsuite/gas/i386/pseudos.s: Add various move, ALU, and FPU
tests.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
* testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d,
testsuite/gas/i386/pseudos.d, testsuite/gas/i386/sse2avx-opts.d,
testsuite/gas/i386/sse2avx-opts-intel.d,
testsuite/gas/i386/x86-64-opts.d,
testsuite/gas/i386/x86-64-opts-intel.d,
testsuite/gas/i386/x86-64-pseudos.d,
testsuite/gas/i386/x86-64-sse2avx-opts.d,
testsuite/gas/i386/x86-64-sse2avx-opts-intel.d: Adjust
expectations.
testsuite/gas/i386/ilp32/x86-64-opts.d,
testsuite/gas/i386/ilp32/x86-64-opts-intel.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Refer to
non-ILP32 output.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -357,7 +357,8 @@ struct _i386_insn
{
dir_encoding_default = 0,
dir_encoding_load,
- dir_encoding_store
+ dir_encoding_store,
+ dir_encoding_swap
} dir_encoding;

/* Prefer 8bit or 32bit displacement in encoding. */
@@ -4494,7 +4495,7 @@ parse_insn (char *line, char *mnemonic)
/* Check if we should swap operand or force 32bit displacement in
encoding. */
if (mnem_p - 2 == dot_p && dot_p[1] == 's')
- i.dir_encoding = dir_encoding_store;
+ i.dir_encoding = dir_encoding_swap;
else if (mnem_p - 3 == dot_p
&& dot_p[1] == 'd'
&& dot_p[2] == '8')
@@ -5674,15 +5675,40 @@ match_template (char mnem_suffix)
continue;
if (!(size_match & MATCH_STRAIGHT))
goto check_reverse;
- /* If we want store form, we reverse direction of operands. */
- if (i.dir_encoding == dir_encoding_store
- && t->opcode_modifier.d)
- goto check_reverse;
+ /* Reverse direction of operands if swapping is possible in the first
+ place (operands need to be symmetric) and
+ - the load form is requested, and the template is a store form,
+ - the store form is requested, and the template is a load form,
+ - the non-default (swapped) form is requested. */
+ overlap1 = operand_type_and (operand_types[0], operand_types[1]);
+ if (t->opcode_modifier.d && i.reg_operands == 2
+ && !operand_type_all_zero (&overlap1))
+ switch (i.dir_encoding)
+ {
+ case dir_encoding_load:
+ if (operand_type_check (operand_types[i.operands - 1], anymem)
+ || operand_types[i.operands - 1].bitfield.regmem)
+ goto check_reverse;
+ break;
+
+ case dir_encoding_store:
+ if (!operand_type_check (operand_types[i.operands - 1], anymem)
+ && !operand_types[i.operands - 1].bitfield.regmem)
+ goto check_reverse;
+ break;
+
+ case dir_encoding_swap:
+ goto check_reverse;
+
+ case dir_encoding_default:
+ break;
+ }
/* Fall through. */

case 3:
/* If we want store form, we skip the current load. */
- if (i.dir_encoding == dir_encoding_store
+ if ((i.dir_encoding == dir_encoding_store
+ || i.dir_encoding == dir_encoding_swap)
&& i.mem_operands == 0
&& t->opcode_modifier.load)
continue;
--- a/gas/testsuite/gas/i386/ilp32/x86-64-opts-intel.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opts-intel.d
@@ -1,327 +1,4 @@
#source: ../x86-64-opts.s
#objdump: -drwMintel,suffix
#name: x86-64 (ILP32) encoding option (Intel mode)
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-#pass
+#dump: ../x86-64-opts-intel.d
--- a/gas/testsuite/gas/i386/ilp32/x86-64-opts.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opts.d
@@ -1,327 +1,4 @@
#source: ../x86-64-opts.s
#objdump: -drwMsuffix
#name: x86-64 (ILP32) encoding option
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-#pass
+#dump: ../x86-64-opts.d
--- a/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d
@@ -2,327 +2,4 @@
#as: -msse2avx
#objdump: -drwMintel,suffix
#name: x86-64 (ILP32) encoding option with -msse2avx (Intel mode)
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-#pass
+#dump: ../x86-64-sse2avx-opts-intel.d
--- a/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d
@@ -2,327 +2,4 @@
#as: -msse2avx
#objdump: -drwMsuffix
#name: x86-64 (ILP32) encoding option with -msse2avx
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-#pass
+#dump: ../x86-64-sse2avx-opts.d
--- a/gas/testsuite/gas/i386/opts-intel.d
+++ b/gas/testsuite/gas/i386/opts-intel.d
@@ -116,6 +116,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -166,6 +194,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1
[ ]*[a-f0-9]+: 00 d1 add cl,dl
--- a/gas/testsuite/gas/i386/opts.d
+++ b/gas/testsuite/gas/i386/opts.d
@@ -115,6 +115,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -165,6 +193,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
--- a/gas/testsuite/gas/i386/opts.s
+++ b/gas/testsuite/gas/i386/opts.s
@@ -114,6 +114,38 @@ _start:
xorl %edx,%ecx
xorl.s %edx,%ecx

+# Tests for moves which cannot be changed
+ mov 0x12345678, %eax
+ mov.s 0x12345678, %eax
+ mov %eax, 0x12345678
+ mov.s %eax, 0x12345678
+ mov %eax, (%edi)
+ mov.s %eax, (%edi)
+ mov (%edi), %eax
+ mov.s (%edi), %eax
+ mov %cr0, %eax
+ mov.s %cr0, %eax
+ mov %eax, %cr7
+ mov.s %eax, %cr7
+ mov %dr0, %eax
+ mov.s %dr0, %eax
+ mov %eax, %dr7
+ mov.s %eax, %dr7
+
+# Tests for op st, st
+ fadd %st, %st
+ fadd.s %st, %st
+ fdiv %st, %st
+ fdiv.s %st, %st
+ fdivr %st, %st
+ fdivr.s %st, %st
+ fmul %st, %st
+ fmul.s %st, %st
+ fsub %st, %st
+ fsub.s %st, %st
+ fsubr %st, %st
+ fsubr.s %st, %st
+
# Tests for op ymm, ymm
vmovapd %ymm4,%ymm6
vmovapd.s %ymm4,%ymm6
@@ -172,6 +204,80 @@ _start:
movq %mm0,%mm4
movq.s %mm0,%mm4

+# Tests for op zmm, zmm
+ vmovapd %zmm4,%zmm6
+ vmovapd.s %zmm4,%zmm6
+ vmovaps %zmm4,%zmm6
+ vmovaps.s %zmm4,%zmm6
+ vmovdqa32 %zmm4,%zmm6
+ vmovdqa32.s %zmm4,%zmm6
+ vmovdqa64 %zmm4,%zmm6
+ vmovdqa64.s %zmm4,%zmm6
+ vmovdqu8 %zmm4,%zmm6
+ vmovdqu8.s %zmm4,%zmm6
+ vmovdqu16 %zmm4,%zmm6
+ vmovdqu16.s %zmm4,%zmm6
+ vmovdqu32 %zmm4,%zmm6
+ vmovdqu32.s %zmm4,%zmm6
+ vmovdqu64 %zmm4,%zmm6
+ vmovdqu64.s %zmm4,%zmm6
+ vmovupd %zmm4,%zmm6
+ vmovupd.s %zmm4,%zmm6
+ vmovups %zmm4,%zmm6
+ vmovups.s %zmm4,%zmm6
+
+# Tests for EVEX forms of op ymm, ymm
+ vmovapd %ymm4,%ymm6{%k7}
+ vmovapd.s %ymm4,%ymm6{%k7}
+ vmovaps %ymm4,%ymm6{%k7}
+ vmovaps.s %ymm4,%ymm6{%k7}
+ vmovdqa32 %ymm4,%ymm6
+ vmovdqa32.s %ymm4,%ymm6
+ vmovdqa64 %ymm4,%ymm6
+ vmovdqa64.s %ymm4,%ymm6
+ vmovdqu8 %ymm4,%ymm6
+ vmovdqu8.s %ymm4,%ymm6
+ vmovdqu16 %ymm4,%ymm6
+ vmovdqu16.s %ymm4,%ymm6
+ vmovdqu32 %ymm4,%ymm6
+ vmovdqu32.s %ymm4,%ymm6
+ vmovdqu64 %ymm4,%ymm6
+ vmovdqu64.s %ymm4,%ymm6
+ vmovupd %ymm4,%ymm6{%k7}
+ vmovupd.s %ymm4,%ymm6{%k7}
+ vmovups %ymm4,%ymm6{%k7}
+ vmovups.s %ymm4,%ymm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm
+ vmovapd %xmm4,%xmm6{%k7}
+ vmovapd.s %xmm4,%xmm6{%k7}
+ vmovaps %xmm4,%xmm6{%k7}
+ vmovaps.s %xmm4,%xmm6{%k7}
+ vmovdqa32 %xmm4,%xmm6
+ vmovdqa32.s %xmm4,%xmm6
+ vmovdqa64 %xmm4,%xmm6
+ vmovdqa64.s %xmm4,%xmm6
+ vmovdqu8 %xmm4,%xmm6
+ vmovdqu8.s %xmm4,%xmm6
+ vmovdqu16 %xmm4,%xmm6
+ vmovdqu16.s %xmm4,%xmm6
+ vmovdqu32 %xmm4,%xmm6
+ vmovdqu32.s %xmm4,%xmm6
+ vmovdqu64 %xmm4,%xmm6
+ vmovdqu64.s %xmm4,%xmm6
+ {evex} vmovq %xmm4,%xmm6
+ {evex} vmovq.s %xmm4,%xmm6
+ vmovupd %xmm4,%xmm6{%k7}
+ vmovupd.s %xmm4,%xmm6{%k7}
+ vmovups %xmm4,%xmm6{%k7}
+ vmovups.s %xmm4,%xmm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm, xmm
+ vmovsd %xmm4,%xmm6,%xmm2{%k7}
+ vmovsd.s %xmm4,%xmm6,%xmm2{%k7}
+ vmovss %xmm4,%xmm6,%xmm2{%k7}
+ vmovss.s %xmm4,%xmm6,%xmm2{%k7}
+
# Tests for op bnd, bnd
bndmov %bnd1,%bnd2
bndmov.s %bnd1,%bnd2
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -22,8 +22,231 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 89 c8 mov %ecx,%eax
- +[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 8b c1 mov %ecx,%eax
+ +[a-f0-9]+: 89 c8 mov %ecx,%eax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 13 c1 adc %ecx,%eax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 03 c1 add %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 23 c1 and %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 3b c1 cmp %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 0b c1 or %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 1b c1 sbb %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 2b c1 sub %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: 33 c1 xor %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: a1 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: a3 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: a1 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: a3 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: 89 07 mov %eax,\(%edi\)
+ +[a-f0-9]+: 8b 07 mov \(%edi\),%eax
+ +[a-f0-9]+: 89 07 mov %eax,\(%edi\)
+ +[a-f0-9]+: 8b 07 mov \(%edi\),%eax
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%edi
+ +[a-f0-9]+: 0f 22 f8 mov %eax,%cr7
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%edi
+ +[a-f0-9]+: 0f 22 f8 mov %eax,%cr7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%edi
+ +[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%edi
+ +[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+ +[a-f0-9]+: 11 07 adc %eax,\(%edi\)
+ +[a-f0-9]+: 13 07 adc \(%edi\),%eax
+ +[a-f0-9]+: 11 07 adc %eax,\(%edi\)
+ +[a-f0-9]+: 13 07 adc \(%edi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%edi\)
+ +[a-f0-9]+: 03 07 add \(%edi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%edi\)
+ +[a-f0-9]+: 03 07 add \(%edi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%edi\)
+ +[a-f0-9]+: 23 07 and \(%edi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%edi\)
+ +[a-f0-9]+: 23 07 and \(%edi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%edi\)
+ +[a-f0-9]+: 3b 07 cmp \(%edi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%edi\)
+ +[a-f0-9]+: 3b 07 cmp \(%edi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%edi\)
+ +[a-f0-9]+: 0b 07 or \(%edi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%edi\)
+ +[a-f0-9]+: 0b 07 or \(%edi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%edi\)
+ +[a-f0-9]+: 1b 07 sbb \(%edi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%edi\)
+ +[a-f0-9]+: 1b 07 sbb \(%edi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%edi\)
+ +[a-f0-9]+: 2b 07 sub \(%edi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%edi\)
+ +[a-f0-9]+: 2b 07 sub \(%edi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%edi\)
+ +[a-f0-9]+: 33 07 xor \(%edi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%edi\)
+ +[a-f0-9]+: 33 07 xor \(%edi\),%eax
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 7f c7 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 29 c7 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 11 c7 movups %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 11 c7 movss %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 29 c7 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 11 c7 movupd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 11 c7 movsd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 7f c7 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7f c7 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f d6 c7 movq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 29 c7 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 29 c7 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 29 c7 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 11 c7 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 11 c7 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 11 c7 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 11 c7 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 11 c7 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 29 c7 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 29 c7 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 29 c7 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 11 c7 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 11 c7 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 11 c7 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 11 c7 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 11 c7 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 7f c7 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 7f c7 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 7f c7 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 7f c7 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 7f c7 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7f c7 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 7f c7 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 7f c7 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 7f c7 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 7f c7 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 7f c7 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7f c7 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
@@ -50,8 +273,8 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 89 c8 mov %ecx,%eax
- +[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 8b c1 mov %ecx,%eax
+ +[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -16,9 +16,239 @@ _start:
{disp32} vmovaps (%eax),%xmm2
{evex} {disp8} vmovaps (%eax),%xmm2
{evex} {disp32} vmovaps (%eax),%xmm2
+
mov %ecx, %eax
{load} mov %ecx, %eax
{store} mov %ecx, %eax
+ adc %ecx, %eax
+ {load} adc %ecx, %eax
+ {store} adc %ecx, %eax
+ add %ecx, %eax
+ {load} add %ecx, %eax
+ {store} add %ecx, %eax
+ and %ecx, %eax
+ {load} and %ecx, %eax
+ {store} and %ecx, %eax
+ cmp %ecx, %eax
+ {load} cmp %ecx, %eax
+ {store} cmp %ecx, %eax
+ or %ecx, %eax
+ {load} or %ecx, %eax
+ {store} or %ecx, %eax
+ sbb %ecx, %eax
+ {load} sbb %ecx, %eax
+ {store} sbb %ecx, %eax
+ sub %ecx, %eax
+ {load} sub %ecx, %eax
+ {store} sub %ecx, %eax
+ xor %ecx, %eax
+ {load} xor %ecx, %eax
+ {store} xor %ecx, %eax
+
+ {load} mov 0x12345678, %eax
+ {load} mov %eax, 0x12345678
+ {store} mov 0x12345678, %eax
+ {store} mov %eax, 0x12345678
+ {load} mov %eax, (%edi)
+ {load} mov (%edi), %eax
+ {store} mov %eax, (%edi)
+ {store} mov (%edi), %eax
+ {load} mov %es, %edi
+ {load} mov %eax, %gs
+ {store} mov %es, %edi
+ {store} mov %eax, %gs
+ {load} mov %cr0, %edi
+ {load} mov %eax, %cr7
+ {store} mov %cr0, %edi
+ {store} mov %eax, %cr7
+ {load} mov %dr0, %edi
+ {load} mov %eax, %dr7
+ {store} mov %dr0, %edi
+ {store} mov %eax, %dr7
+ {load} adc %eax, (%edi)
+ {load} adc (%edi), %eax
+ {store} adc %eax, (%edi)
+ {store} adc (%edi), %eax
+ {load} add %eax, (%edi)
+ {load} add (%edi), %eax
+ {store} add %eax, (%edi)
+ {store} add (%edi), %eax
+ {load} and %eax, (%edi)
+ {load} and (%edi), %eax
+ {store} and %eax, (%edi)
+ {store} and (%edi), %eax
+ {load} cmp %eax, (%edi)
+ {load} cmp (%edi), %eax
+ {store} cmp %eax, (%edi)
+ {store} cmp (%edi), %eax
+ {load} or %eax, (%edi)
+ {load} or (%edi), %eax
+ {store} or %eax, (%edi)
+ {store} or (%edi), %eax
+ {load} sbb %eax, (%edi)
+ {load} sbb (%edi), %eax
+ {store} sbb %eax, (%edi)
+ {store} sbb (%edi), %eax
+ {load} sub %eax, (%edi)
+ {load} sub (%edi), %eax
+ {store} sub %eax, (%edi)
+ {store} sub (%edi), %eax
+ {load} xor %eax, (%edi)
+ {load} xor (%edi), %eax
+ {store} xor %eax, (%edi)
+ {store} xor (%edi), %eax
+
+ fadd %st, %st
+ {load} fadd %st, %st
+ {store} fadd %st, %st
+ fdiv %st, %st
+ {load} fdiv %st, %st
+ {store} fdiv %st, %st
+ fdivr %st, %st
+ {load} fdivr %st, %st
+ {store} fdivr %st, %st
+ fmul %st, %st
+ {load} fmul %st, %st
+ {store} fmul %st, %st
+ fsub %st, %st
+ {load} fsub %st, %st
+ {store} fsub %st, %st
+ fsubr %st, %st
+ {load} fsubr %st, %st
+ {store} fsubr %st, %st
+
+ movq %mm0, %mm7
+ {load} movq %mm0, %mm7
+ {store} movq %mm0, %mm7
+
+ movaps %xmm0, %xmm7
+ {load} movaps %xmm0, %xmm7
+ {store} movaps %xmm0, %xmm7
+ movups %xmm0, %xmm7
+ {load} movups %xmm0, %xmm7
+ {store} movups %xmm0, %xmm7
+ movss %xmm0, %xmm7
+ {load} movss %xmm0, %xmm7
+ {store} movss %xmm0, %xmm7
+ movapd %xmm0, %xmm7
+ {load} movapd %xmm0, %xmm7
+ {store} movapd %xmm0, %xmm7
+ movupd %xmm0, %xmm7
+ {load} movupd %xmm0, %xmm7
+ {store} movupd %xmm0, %xmm7
+ movsd %xmm0, %xmm7
+ {load} movsd %xmm0, %xmm7
+ {store} movsd %xmm0, %xmm7
+ movdqa %xmm0, %xmm7
+ {load} movdqa %xmm0, %xmm7
+ {store} movdqa %xmm0, %xmm7
+ movdqu %xmm0, %xmm7
+ {load} movdqu %xmm0, %xmm7
+ {store} movdqu %xmm0, %xmm7
+ movq %xmm0, %xmm7
+ {load} movq %xmm0, %xmm7
+ {store} movq %xmm0, %xmm7
+ vmovaps %xmm0, %xmm7
+ {load} vmovaps %xmm0, %xmm7
+ {store} vmovaps %xmm0, %xmm7
+ vmovaps %zmm0, %zmm7
+ {load} vmovaps %zmm0, %zmm7
+ {store} vmovaps %zmm0, %zmm7
+ vmovaps %xmm0, %xmm7{%k7}
+ {load} vmovaps %xmm0, %xmm7{%k7}
+ {store} vmovaps %xmm0, %xmm7{%k7}
+ vmovups %zmm0, %zmm7
+ {load} vmovups %zmm0, %zmm7
+ {store} vmovups %zmm0, %zmm7
+ vmovups %xmm0, %xmm7
+ {load} vmovups %xmm0, %xmm7
+ {store} vmovups %xmm0, %xmm7
+ vmovups %xmm0, %xmm7{%k7}
+ {load} vmovups %xmm0, %xmm7{%k7}
+ {store} vmovups %xmm0, %xmm7{%k7}
+ vmovss %xmm0, %xmm1, %xmm7
+ {load} vmovss %xmm0, %xmm1, %xmm7
+ {store} vmovss %xmm0, %xmm1, %xmm7
+ vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ vmovapd %xmm0, %xmm7
+ {load} vmovapd %xmm0, %xmm7
+ {store} vmovapd %xmm0, %xmm7
+ vmovapd %zmm0, %zmm7
+ {load} vmovapd %zmm0, %zmm7
+ {store} vmovapd %zmm0, %zmm7
+ vmovapd %xmm0, %xmm7{%k7}
+ {load} vmovapd %xmm0, %xmm7{%k7}
+ {store} vmovapd %xmm0, %xmm7{%k7}
+ vmovupd %xmm0, %xmm7
+ {load} vmovupd %xmm0, %xmm7
+ {store} vmovupd %xmm0, %xmm7
+ vmovupd %zmm0, %zmm7
+ {load} vmovupd %zmm0, %zmm7
+ {store} vmovupd %zmm0, %zmm7
+ vmovupd %xmm0, %xmm7{%k7}
+ {load} vmovupd %xmm0, %xmm7{%k7}
+ {store} vmovupd %xmm0, %xmm7{%k7}
+ vmovsd %xmm0, %xmm1, %xmm7
+ {load} vmovsd %xmm0, %xmm1, %xmm7
+ {store} vmovsd %xmm0, %xmm1, %xmm7
+ vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ vmovdqa %xmm0, %xmm7
+ {load} vmovdqa %xmm0, %xmm7
+ {store} vmovdqa %xmm0, %xmm7
+ vmovdqa32 %zmm0, %zmm7
+ {load} vmovdqa32 %zmm0, %zmm7
+ {store} vmovdqa32 %zmm0, %zmm7
+ vmovdqa32 %xmm0, %xmm7
+ {load} vmovdqa32 %xmm0, %xmm7
+ {store} vmovdqa32 %xmm0, %xmm7
+ vmovdqa64 %zmm0, %zmm7
+ {load} vmovdqa64 %zmm0, %zmm7
+ {store} vmovdqa64 %zmm0, %zmm7
+ vmovdqa64 %xmm0, %xmm7
+ {load} vmovdqa64 %xmm0, %xmm7
+ {store} vmovdqa64 %xmm0, %xmm7
+ vmovdqu %xmm0, %xmm7
+ {load} vmovdqu %xmm0, %xmm7
+ {store} vmovdqu %xmm0, %xmm7
+ vmovdqu8 %zmm0, %zmm7
+ {load} vmovdqu8 %zmm0, %zmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu8 %xmm0, %xmm7
+ {load} vmovdqu8 %xmm0, %xmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu16 %zmm0, %zmm7
+ {load} vmovdqu16 %zmm0, %zmm7
+ {store} vmovdqu16 %zmm0, %zmm7
+ vmovdqu16 %xmm0, %xmm7
+ {load} vmovdqu16 %xmm0, %xmm7
+ {store} vmovdqu16 %xmm0, %xmm7
+ vmovdqu32 %zmm0, %zmm7
+ {load} vmovdqu32 %zmm0, %zmm7
+ {store} vmovdqu32 %zmm0, %zmm7
+ vmovdqu32 %xmm0, %xmm7
+ {load} vmovdqu32 %xmm0, %xmm7
+ {store} vmovdqu32 %xmm0, %xmm7
+ vmovdqu64 %zmm0, %zmm7
+ {load} vmovdqu64 %zmm0, %zmm7
+ {store} vmovdqu64 %zmm0, %zmm7
+ vmovdqu64 %xmm0, %xmm7
+ {load} vmovdqu64 %xmm0, %xmm7
+ {store} vmovdqu64 %xmm0, %xmm7
+ vmovq %xmm0, %xmm7
+ {load} vmovq %xmm0, %xmm7
+ {store} vmovq %xmm0, %xmm7
+ {evex} vmovq %xmm0, %xmm7
+ {load} {evex} vmovq %xmm0, %xmm7
+ {store} {evex} vmovq %xmm0, %xmm7
+
+ bndmov %bnd3, %bnd0
+ {load} bndmov %bnd3, %bnd0
+ {store} bndmov %bnd3, %bnd0
+
movaps (%eax),%xmm2
{load} movaps (%eax),%xmm2
{store} movaps (%eax),%xmm2
--- a/gas/testsuite/gas/i386/sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/sse2avx-opts-intel.d
@@ -117,6 +117,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -167,6 +195,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1
[ ]*[a-f0-9]+: 00 d1 add cl,dl
--- a/gas/testsuite/gas/i386/sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/sse2avx-opts.d
@@ -117,6 +117,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -167,6 +195,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
--- a/gas/testsuite/gas/i386/x86-64-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-opts-intel.d
@@ -152,6 +152,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -202,6 +238,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov bnd3,bnd0
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s bnd3,bnd0
[ ]*[a-f0-9]+: 00 d1 add cl,dl
[ ]*[a-f0-9]+: 02 ca add.s cl,dl
[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
--- a/gas/testsuite/gas/i386/x86-64-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-opts.d
@@ -151,6 +151,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -201,6 +237,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov %bnd0,%bnd3
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s %bnd0,%bnd3
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
--- a/gas/testsuite/gas/i386/x86-64-opts.s
+++ b/gas/testsuite/gas/i386/x86-64-opts.s
@@ -150,6 +150,46 @@ _start:
xorq %rdx,%rcx
xorq.s %rdx,%rcx

+# Tests for moves which cannot be changed
+ mov 0x12345678, %eax
+ mov.s 0x12345678, %eax
+ mov %eax, 0x12345678
+ mov.s %eax, 0x12345678
+ mov 0x123456789abcdef0, %eax
+ mov.s 0x123456789abcdef0, %eax
+ mov %eax, 0x123456789abcdef0
+ mov.s %eax, 0x123456789abcdef0
+ movabs 0x123456789abcdef0, %eax
+ movabs.s 0x123456789abcdef0, %eax
+ movabs %eax, 0x123456789abcdef0
+ movabs.s %eax, 0x123456789abcdef0
+ mov %eax, (%rdi)
+ mov.s %eax, (%rdi)
+ mov (%rdi), %eax
+ mov.s (%rdi), %eax
+ mov %cr0, %rax
+ mov.s %cr0, %rax
+ mov %rax, %cr7
+ mov.s %rax, %cr7
+ mov %dr0, %rax
+ mov.s %dr0, %rax
+ mov %rax, %dr7
+ mov.s %rax, %dr7
+
+# Tests for op st, st
+ fadd %st, %st
+ fadd.s %st, %st
+ fdiv %st, %st
+ fdiv.s %st, %st
+ fdivr %st, %st
+ fdivr.s %st, %st
+ fmul %st, %st
+ fmul.s %st, %st
+ fsub %st, %st
+ fsub.s %st, %st
+ fsubr %st, %st
+ fsubr.s %st, %st
+
# Tests for op ymm, ymm
vmovapd %ymm4,%ymm6
vmovapd.s %ymm4,%ymm6
@@ -208,6 +248,84 @@ _start:
movq %mm0,%mm4
movq.s %mm0,%mm4

+# Tests for op zmm, zmm
+ vmovapd %zmm4,%zmm6
+ vmovapd.s %zmm4,%zmm6
+ vmovaps %zmm4,%zmm6
+ vmovaps.s %zmm4,%zmm6
+ vmovdqa32 %zmm4,%zmm6
+ vmovdqa32.s %zmm4,%zmm6
+ vmovdqa64 %zmm4,%zmm6
+ vmovdqa64.s %zmm4,%zmm6
+ vmovdqu8 %zmm4,%zmm6
+ vmovdqu8.s %zmm4,%zmm6
+ vmovdqu16 %zmm4,%zmm6
+ vmovdqu16.s %zmm4,%zmm6
+ vmovdqu32 %zmm4,%zmm6
+ vmovdqu32.s %zmm4,%zmm6
+ vmovdqu64 %zmm4,%zmm6
+ vmovdqu64.s %zmm4,%zmm6
+ vmovupd %zmm4,%zmm6
+ vmovupd.s %zmm4,%zmm6
+ vmovups %zmm4,%zmm6
+ vmovups.s %zmm4,%zmm6
+
+# Tests for EVEX forms of op ymm, ymm
+ vmovapd %ymm4,%ymm6{%k7}
+ vmovapd.s %ymm4,%ymm6{%k7}
+ vmovaps %ymm4,%ymm6{%k7}
+ vmovaps.s %ymm4,%ymm6{%k7}
+ vmovdqa32 %ymm4,%ymm6
+ vmovdqa32.s %ymm4,%ymm6
+ vmovdqa64 %ymm4,%ymm6
+ vmovdqa64.s %ymm4,%ymm6
+ vmovdqu8 %ymm4,%ymm6
+ vmovdqu8.s %ymm4,%ymm6
+ vmovdqu16 %ymm4,%ymm6
+ vmovdqu16.s %ymm4,%ymm6
+ vmovdqu32 %ymm4,%ymm6
+ vmovdqu32.s %ymm4,%ymm6
+ vmovdqu64 %ymm4,%ymm6
+ vmovdqu64.s %ymm4,%ymm6
+ vmovupd %ymm4,%ymm6{%k7}
+ vmovupd.s %ymm4,%ymm6{%k7}
+ vmovups %ymm4,%ymm6{%k7}
+ vmovups.s %ymm4,%ymm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm
+ vmovapd %xmm4,%xmm6{%k7}
+ vmovapd.s %xmm4,%xmm6{%k7}
+ vmovaps %xmm4,%xmm6{%k7}
+ vmovaps.s %xmm4,%xmm6{%k7}
+ vmovdqa32 %xmm4,%xmm6
+ vmovdqa32.s %xmm4,%xmm6
+ vmovdqa64 %xmm4,%xmm6
+ vmovdqa64.s %xmm4,%xmm6
+ vmovdqu8 %xmm4,%xmm6
+ vmovdqu8.s %xmm4,%xmm6
+ vmovdqu16 %xmm4,%xmm6
+ vmovdqu16.s %xmm4,%xmm6
+ vmovdqu32 %xmm4,%xmm6
+ vmovdqu32.s %xmm4,%xmm6
+ vmovdqu64 %xmm4,%xmm6
+ vmovdqu64.s %xmm4,%xmm6
+ {evex} vmovq %xmm4,%xmm6
+ {evex} vmovq.s %xmm4,%xmm6
+ vmovupd %xmm4,%xmm6{%k7}
+ vmovupd.s %xmm4,%xmm6{%k7}
+ vmovups %xmm4,%xmm6{%k7}
+ vmovups.s %xmm4,%xmm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm, xmm
+ vmovsd %xmm4,%xmm6,%xmm2{%k7}
+ vmovsd.s %xmm4,%xmm6,%xmm2{%k7}
+ vmovss %xmm4,%xmm6,%xmm2{%k7}
+ vmovss.s %xmm4,%xmm6,%xmm2{%k7}
+
+# Tests for op bnd, bnd
+ bndmov %bnd0, %bnd3
+ bndmov.s %bnd0, %bnd3
+
.intel_syntax noprefix

# Tests for op reg, reg
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -22,8 +22,239 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 48 89 c8 mov %rcx,%rax
- +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+[a-f0-9]+: 48 8b c1 mov %rcx,%rax
+ +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 13 c1 adc %ecx,%eax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 03 c1 add %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 23 c1 and %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 3b c1 cmp %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 0b c1 or %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 1b c1 sbb %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 2b c1 sub %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: 33 c1 xor %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: 8b 04 25 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: 89 04 25 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: 8b 04 25 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: 89 04 25 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: 89 07 mov %eax,\(%rdi\)
+ +[a-f0-9]+: 8b 07 mov \(%rdi\),%eax
+ +[a-f0-9]+: 89 07 mov %eax,\(%rdi\)
+ +[a-f0-9]+: 8b 07 mov \(%rdi\),%eax
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%rdi
+ +[a-f0-9]+: 0f 22 f8 mov %rax,%cr7
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%rdi
+ +[a-f0-9]+: 0f 22 f8 mov %rax,%cr7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%rdi
+ +[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%rdi
+ +[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+ +[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
+ +[a-f0-9]+: 13 07 adc \(%rdi\),%eax
+ +[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
+ +[a-f0-9]+: 13 07 adc \(%rdi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%rdi\)
+ +[a-f0-9]+: 03 07 add \(%rdi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%rdi\)
+ +[a-f0-9]+: 03 07 add \(%rdi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%rdi\)
+ +[a-f0-9]+: 23 07 and \(%rdi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%rdi\)
+ +[a-f0-9]+: 23 07 and \(%rdi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%rdi\)
+ +[a-f0-9]+: 3b 07 cmp \(%rdi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%rdi\)
+ +[a-f0-9]+: 3b 07 cmp \(%rdi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%rdi\)
+ +[a-f0-9]+: 0b 07 or \(%rdi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%rdi\)
+ +[a-f0-9]+: 0b 07 or \(%rdi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%rdi\)
+ +[a-f0-9]+: 1b 07 sbb \(%rdi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%rdi\)
+ +[a-f0-9]+: 1b 07 sbb \(%rdi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%rdi\)
+ +[a-f0-9]+: 2b 07 sub \(%rdi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%rdi\)
+ +[a-f0-9]+: 2b 07 sub \(%rdi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%rdi\)
+ +[a-f0-9]+: 33 07 xor \(%rdi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%rdi\)
+ +[a-f0-9]+: 33 07 xor \(%rdi\),%eax
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 7f c7 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 29 c7 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 11 c7 movups %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 11 c7 movss %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 29 c7 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 11 c7 movupd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 11 c7 movsd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 7f c7 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7f c7 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f d6 c7 movq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 29 c7 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 29 c7 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 29 c7 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 11 c7 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 11 c7 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 11 c7 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 11 c7 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 11 c7 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 29 c7 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 29 c7 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 29 c7 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 11 c7 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 11 c7 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 11 c7 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 11 c7 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 11 c7 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 7f c7 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 7f c7 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 7f c7 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 7f c7 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 7f c7 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7f c7 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 7f c7 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 7f c7 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 7f c7 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 7f c7 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 7f c7 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7f c7 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
@@ -63,8 +294,8 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 48 89 c8 mov %rcx,%rax
- +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+[a-f0-9]+: 48 8b c1 mov %rcx,%rax
+ +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -16,9 +16,247 @@ _start:
{disp32} vmovaps (%rax),%xmm2
{evex} {disp8} vmovaps (%rax),%xmm2
{evex} {disp32} vmovaps (%rax),%xmm2
+
mov %rcx, %rax
{load} mov %rcx, %rax
{store} mov %rcx, %rax
+ adc %ecx, %eax
+ {load} adc %ecx, %eax
+ {store} adc %ecx, %eax
+ add %ecx, %eax
+ {load} add %ecx, %eax
+ {store} add %ecx, %eax
+ and %ecx, %eax
+ {load} and %ecx, %eax
+ {store} and %ecx, %eax
+ cmp %ecx, %eax
+ {load} cmp %ecx, %eax
+ {store} cmp %ecx, %eax
+ or %ecx, %eax
+ {load} or %ecx, %eax
+ {store} or %ecx, %eax
+ sbb %ecx, %eax
+ {load} sbb %ecx, %eax
+ {store} sbb %ecx, %eax
+ sub %ecx, %eax
+ {load} sub %ecx, %eax
+ {store} sub %ecx, %eax
+ xor %ecx, %eax
+ {load} xor %ecx, %eax
+ {store} xor %ecx, %eax
+
+ {load} mov 0x12345678, %eax
+ {load} mov %eax, 0x12345678
+ {store} mov 0x12345678, %eax
+ {store} mov %eax, 0x12345678
+ {load} mov 0x123456789abcdef0, %eax
+ {load} mov %eax, 0x123456789abcdef0
+ {store} mov 0x123456789abcdef0, %eax
+ {store} mov %eax, 0x123456789abcdef0
+ {load} movabs 0x123456789abcdef0, %eax
+ {load} movabs %eax, 0x123456789abcdef0
+ {store} movabs 0x123456789abcdef0, %eax
+ {store} movabs %eax, 0x123456789abcdef0
+ {load} mov %eax, (%rdi)
+ {load} mov (%rdi), %eax
+ {store} mov %eax, (%rdi)
+ {store} mov (%rdi), %eax
+ {load} mov %es, %edi
+ {load} mov %eax, %gs
+ {store} mov %es, %edi
+ {store} mov %eax, %gs
+ {load} mov %cr0, %rdi
+ {load} mov %rax, %cr7
+ {store} mov %cr0, %rdi
+ {store} mov %rax, %cr7
+ {load} mov %dr0, %rdi
+ {load} mov %rax, %dr7
+ {store} mov %dr0, %rdi
+ {store} mov %rax, %dr7
+ {load} adc %eax, (%rdi)
+ {load} adc (%rdi), %eax
+ {store} adc %eax, (%rdi)
+ {store} adc (%rdi), %eax
+ {load} add %eax, (%rdi)
+ {load} add (%rdi), %eax
+ {store} add %eax, (%rdi)
+ {store} add (%rdi), %eax
+ {load} and %eax, (%rdi)
+ {load} and (%rdi), %eax
+ {store} and %eax, (%rdi)
+ {store} and (%rdi), %eax
+ {load} cmp %eax, (%rdi)
+ {load} cmp (%rdi), %eax
+ {store} cmp %eax, (%rdi)
+ {store} cmp (%rdi), %eax
+ {load} or %eax, (%rdi)
+ {load} or (%rdi), %eax
+ {store} or %eax, (%rdi)
+ {store} or (%rdi), %eax
+ {load} sbb %eax, (%rdi)
+ {load} sbb (%rdi), %eax
+ {store} sbb %eax, (%rdi)
+ {store} sbb (%rdi), %eax
+ {load} sub %eax, (%rdi)
+ {load} sub (%rdi), %eax
+ {store} sub %eax, (%rdi)
+ {store} sub (%rdi), %eax
+ {load} xor %eax, (%rdi)
+ {load} xor (%rdi), %eax
+ {store} xor %eax, (%rdi)
+ {store} xor (%rdi), %eax
+
+ fadd %st, %st
+ {load} fadd %st, %st
+ {store} fadd %st, %st
+ fdiv %st, %st
+ {load} fdiv %st, %st
+ {store} fdiv %st, %st
+ fdivr %st, %st
+ {load} fdivr %st, %st
+ {store} fdivr %st, %st
+ fmul %st, %st
+ {load} fmul %st, %st
+ {store} fmul %st, %st
+ fsub %st, %st
+ {load} fsub %st, %st
+ {store} fsub %st, %st
+ fsubr %st, %st
+ {load} fsubr %st, %st
+ {store} fsubr %st, %st
+
+ movq %mm0, %mm7
+ {load} movq %mm0, %mm7
+ {store} movq %mm0, %mm7
+
+ movaps %xmm0, %xmm7
+ {load} movaps %xmm0, %xmm7
+ {store} movaps %xmm0, %xmm7
+ movups %xmm0, %xmm7
+ {load} movups %xmm0, %xmm7
+ {store} movups %xmm0, %xmm7
+ movss %xmm0, %xmm7
+ {load} movss %xmm0, %xmm7
+ {store} movss %xmm0, %xmm7
+ movapd %xmm0, %xmm7
+ {load} movapd %xmm0, %xmm7
+ {store} movapd %xmm0, %xmm7
+ movupd %xmm0, %xmm7
+ {load} movupd %xmm0, %xmm7
+ {store} movupd %xmm0, %xmm7
+ movsd %xmm0, %xmm7
+ {load} movsd %xmm0, %xmm7
+ {store} movsd %xmm0, %xmm7
+ movdqa %xmm0, %xmm7
+ {load} movdqa %xmm0, %xmm7
+ {store} movdqa %xmm0, %xmm7
+ movdqu %xmm0, %xmm7
+ {load} movdqu %xmm0, %xmm7
+ {store} movdqu %xmm0, %xmm7
+ movq %xmm0, %xmm7
+ {load} movq %xmm0, %xmm7
+ {store} movq %xmm0, %xmm7
+ vmovaps %xmm0, %xmm7
+ {load} vmovaps %xmm0, %xmm7
+ {store} vmovaps %xmm0, %xmm7
+ vmovaps %zmm0, %zmm7
+ {load} vmovaps %zmm0, %zmm7
+ {store} vmovaps %zmm0, %zmm7
+ vmovaps %xmm0, %xmm7{%k7}
+ {load} vmovaps %xmm0, %xmm7{%k7}
+ {store} vmovaps %xmm0, %xmm7{%k7}
+ vmovups %zmm0, %zmm7
+ {load} vmovups %zmm0, %zmm7
+ {store} vmovups %zmm0, %zmm7
+ vmovups %xmm0, %xmm7
+ {load} vmovups %xmm0, %xmm7
+ {store} vmovups %xmm0, %xmm7
+ vmovups %xmm0, %xmm7{%k7}
+ {load} vmovups %xmm0, %xmm7{%k7}
+ {store} vmovups %xmm0, %xmm7{%k7}
+ vmovss %xmm0, %xmm1, %xmm7
+ {load} vmovss %xmm0, %xmm1, %xmm7
+ {store} vmovss %xmm0, %xmm1, %xmm7
+ vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ vmovapd %xmm0, %xmm7
+ {load} vmovapd %xmm0, %xmm7
+ {store} vmovapd %xmm0, %xmm7
+ vmovapd %zmm0, %zmm7
+ {load} vmovapd %zmm0, %zmm7
+ {store} vmovapd %zmm0, %zmm7
+ vmovapd %xmm0, %xmm7{%k7}
+ {load} vmovapd %xmm0, %xmm7{%k7}
+ {store} vmovapd %xmm0, %xmm7{%k7}
+ vmovupd %xmm0, %xmm7
+ {load} vmovupd %xmm0, %xmm7
+ {store} vmovupd %xmm0, %xmm7
+ vmovupd %zmm0, %zmm7
+ {load} vmovupd %zmm0, %zmm7
+ {store} vmovupd %zmm0, %zmm7
+ vmovupd %xmm0, %xmm7{%k7}
+ {load} vmovupd %xmm0, %xmm7{%k7}
+ {store} vmovupd %xmm0, %xmm7{%k7}
+ vmovsd %xmm0, %xmm1, %xmm7
+ {load} vmovsd %xmm0, %xmm1, %xmm7
+ {store} vmovsd %xmm0, %xmm1, %xmm7
+ vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ vmovdqa %xmm0, %xmm7
+ {load} vmovdqa %xmm0, %xmm7
+ {store} vmovdqa %xmm0, %xmm7
+ vmovdqa32 %zmm0, %zmm7
+ {load} vmovdqa32 %zmm0, %zmm7
+ {store} vmovdqa32 %zmm0, %zmm7
+ vmovdqa32 %xmm0, %xmm7
+ {load} vmovdqa32 %xmm0, %xmm7
+ {store} vmovdqa32 %xmm0, %xmm7
+ vmovdqa64 %zmm0, %zmm7
+ {load} vmovdqa64 %zmm0, %zmm7
+ {store} vmovdqa64 %zmm0, %zmm7
+ vmovdqa64 %xmm0, %xmm7
+ {load} vmovdqa64 %xmm0, %xmm7
+ {store} vmovdqa64 %xmm0, %xmm7
+ vmovdqu %xmm0, %xmm7
+ {load} vmovdqu %xmm0, %xmm7
+ {store} vmovdqu %xmm0, %xmm7
+ vmovdqu8 %zmm0, %zmm7
+ {load} vmovdqu8 %zmm0, %zmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu8 %xmm0, %xmm7
+ {load} vmovdqu8 %xmm0, %xmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu16 %zmm0, %zmm7
+ {load} vmovdqu16 %zmm0, %zmm7
+ {store} vmovdqu16 %zmm0, %zmm7
+ vmovdqu16 %xmm0, %xmm7
+ {load} vmovdqu16 %xmm0, %xmm7
+ {store} vmovdqu16 %xmm0, %xmm7
+ vmovdqu32 %zmm0, %zmm7
+ {load} vmovdqu32 %zmm0, %zmm7
+ {store} vmovdqu32 %zmm0, %zmm7
+ vmovdqu32 %xmm0, %xmm7
+ {load} vmovdqu32 %xmm0, %xmm7
+ {store} vmovdqu32 %xmm0, %xmm7
+ vmovdqu64 %zmm0, %zmm7
+ {load} vmovdqu64 %zmm0, %zmm7
+ {store} vmovdqu64 %zmm0, %zmm7
+ vmovdqu64 %xmm0, %xmm7
+ {load} vmovdqu64 %xmm0, %xmm7
+ {store} vmovdqu64 %xmm0, %xmm7
+ vmovq %xmm0, %xmm7
+ {load} vmovq %xmm0, %xmm7
+ {store} vmovq %xmm0, %xmm7
+ {evex} vmovq %xmm0, %xmm7
+ {load} {evex} vmovq %xmm0, %xmm7
+ {store} {evex} vmovq %xmm0, %xmm7
+
+ bndmov %bnd3, %bnd0
+ {load} bndmov %bnd3, %bnd0
+ {store} bndmov %bnd3, %bnd0
+
movaps (%rax),%xmm2
{load} movaps (%rax),%xmm2
{store} movaps (%rax),%xmm2
--- a/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
@@ -153,6 +153,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -203,6 +239,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov bnd3,bnd0
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s bnd3,bnd0
[ ]*[a-f0-9]+: 00 d1 add cl,dl
[ ]*[a-f0-9]+: 02 ca add.s cl,dl
[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
--- a/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
@@ -153,6 +153,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -203,6 +239,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov %bnd0,%bnd3
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s %bnd0,%bnd3
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
H.J. Lu
2018-08-02 12:19:57 UTC
Permalink
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
--
H.J.
Jan Beulich
2018-08-02 12:38:05 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
There's no {swap} prefix. I've just (verbally) assigned the meaning of
"swap" to the .s suffix (which is the behavior it always had afaict,
rather than forcing a store to be used, as one could have implied from
it being 's' and it having had the same behavior as {store}, just that
the behavior was clearly wrong for {store}). This isn't a very good
association, but I couldn't come up with anything better that would
fit the 's'.

Please take a look at the testsuite adjustments - this gives a pretty
good picture, and you'll notice that uses of .s continue to behave as
before. The adjustments (beyond the various additions) were for
{load} and/or {store} now behaving according to their names.

Jan
H.J. Lu
2018-08-02 12:51:41 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
There's no {swap} prefix. I've just (verbally) assigned the meaning of
"swap" to the .s suffix (which is the behavior it always had afaict,
rather than forcing a store to be used, as one could have implied from
it being 's' and it having had the same behavior as {store}, just that
the behavior was clearly wrong for {store}). This isn't a very good
association, but I couldn't come up with anything better that would
fit the 's'.
Please take a look at the testsuite adjustments - this gives a pretty
good picture, and you'll notice that uses of .s continue to behave as
before. The adjustments (beyond the various additions) were for
{load} and/or {store} now behaving according to their names.
There are many test changes, Can you list a couple for before and
after comparison?
--
H.J.
Jan Beulich
2018-08-02 14:00:06 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
There's no {swap} prefix. I've just (verbally) assigned the meaning of
"swap" to the .s suffix (which is the behavior it always had afaict,
rather than forcing a store to be used, as one could have implied from
it being 's' and it having had the same behavior as {store}, just that
the behavior was clearly wrong for {store}). This isn't a very good
association, but I couldn't come up with anything better that would
fit the 's'.
Please take a look at the testsuite adjustments - this gives a pretty
good picture, and you'll notice that uses of .s continue to behave as
before. The adjustments (beyond the various additions) were for
{load} and/or {store} now behaving according to their names.
There are many test changes, Can you list a couple for before and
after comparison?
I'm afraid I don't really understand what you're after. Looking at the
patch makes pretty obvious what the very few changes are that aren't
plain additions. Iirc there were only two mov-es with {load} (or was
it {store}) prefix where the output changed.

Jan
H.J. Lu
2018-08-02 15:04:48 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
There's no {swap} prefix. I've just (verbally) assigned the meaning of
"swap" to the .s suffix (which is the behavior it always had afaict,
rather than forcing a store to be used, as one could have implied from
it being 's' and it having had the same behavior as {store}, just that
the behavior was clearly wrong for {store}). This isn't a very good
association, but I couldn't come up with anything better that would
fit the 's'.
Please take a look at the testsuite adjustments - this gives a pretty
good picture, and you'll notice that uses of .s continue to behave as
before. The adjustments (beyond the various additions) were for
{load} and/or {store} now behaving according to their names.
There are many test changes, Can you list a couple for before and
after comparison?
I'm afraid I don't really understand what you're after. Looking at the
patch makes pretty obvious what the very few changes are that aren't
plain additions. Iirc there were only two mov-es with {load} (or was
it {store}) prefix where the output changed.
I prefer not to make any changes for the `s' prefix. It is very hard to
tell what changed in disassembler output since your patch removes
and adds a large chunk of disassembler output.
--
H.J.
Jan Beulich
2018-08-02 16:05:58 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
There's no {swap} prefix. I've just (verbally) assigned the meaning of
"swap" to the .s suffix (which is the behavior it always had afaict,
rather than forcing a store to be used, as one could have implied from
it being 's' and it having had the same behavior as {store}, just that
the behavior was clearly wrong for {store}). This isn't a very good
association, but I couldn't come up with anything better that would
fit the 's'.
Please take a look at the testsuite adjustments - this gives a pretty
good picture, and you'll notice that uses of .s continue to behave as
before. The adjustments (beyond the various additions) were for
{load} and/or {store} now behaving according to their names.
There are many test changes, Can you list a couple for before and
after comparison?
I'm afraid I don't really understand what you're after. Looking at the
patch makes pretty obvious what the very few changes are that aren't
plain additions. Iirc there were only two mov-es with {load} (or was
it {store}) prefix where the output changed.
I prefer not to make any changes for the `s' prefix. It is very hard to
tell what changed in disassembler output since your patch removes
and adds a large chunk of disassembler output.
Where? There is a total of two lines each replaced in
testsuite/gas/i386/pseudos.d and testsuite/gas/i386/x86-64-pseudos.d.
For the other removal - there's none really, I'm only re-using other .d
files instead of replicating the additions:

testsuite/gas/i386/ilp32/x86-64-opts.d,
testsuite/gas/i386/ilp32/x86-64-opts-intel.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Refer to
non-ILP32 output.

It is entirely unclear to me why, if we already have to have tests which
are entirely indifferent between ILP32 and LP64, these tests hadn't
been written without such redundancy in the first place. I'm not really
eager to do so, but I could of course split out that part of the change.

Jan
H.J. Lu
2018-08-02 16:43:05 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
I prefer not to change the behavior of the `.s' suffix, unless it is to fix
the wrong encoding. I don't see the need for the 'swap' pseudo prefix.
If the programmer doesn't care load/store encoding, "swap" isn't really
useful.
There's no {swap} prefix. I've just (verbally) assigned the meaning of
"swap" to the .s suffix (which is the behavior it always had afaict,
rather than forcing a store to be used, as one could have implied from
it being 's' and it having had the same behavior as {store}, just that
the behavior was clearly wrong for {store}). This isn't a very good
association, but I couldn't come up with anything better that would
fit the 's'.
Please take a look at the testsuite adjustments - this gives a pretty
good picture, and you'll notice that uses of .s continue to behave as
before. The adjustments (beyond the various additions) were for
{load} and/or {store} now behaving according to their names.
There are many test changes, Can you list a couple for before and
after comparison?
I'm afraid I don't really understand what you're after. Looking at the
patch makes pretty obvious what the very few changes are that aren't
plain additions. Iirc there were only two mov-es with {load} (or was
it {store}) prefix where the output changed.
I prefer not to make any changes for the `s' prefix. It is very hard to
tell what changed in disassembler output since your patch removes
and adds a large chunk of disassembler output.
Where? There is a total of two lines each replaced in
testsuite/gas/i386/pseudos.d and testsuite/gas/i386/x86-64-pseudos.d.
For the other removal - there's none really, I'm only re-using other .d
testsuite/gas/i386/ilp32/x86-64-opts.d,
testsuite/gas/i386/ilp32/x86-64-opts-intel.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Refer to
non-ILP32 output.
It is entirely unclear to me why, if we already have to have tests which
are entirely indifferent between ILP32 and LP64, these tests hadn't
been written without such redundancy in the first place. I'm not really
eager to do so, but I could of course split out that part of the change.
I deprecated ".s", ".d8" and ".d32" when I added {load} and {store} prefixes:

commit 86fa6981e7487e2c2df4337aa75ed2d93c32eaf2
Author: H.J. Lu <***@gmail.com>
Date: Thu Mar 9 09:58:46 2017 -0800

X86: Add pseudo prefixes to control encoding

Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.

gas/

* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"

Please don't make any changes to the deprecated ".s".
--
H.J.
Jan Beulich
2018-08-03 07:08:26 UTC
Permalink
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.

And btw - it's nice to have all these pseudo prefixes, if only they
had actually worked half way correctly from the very beginning.
And I'm already leaving aside the case of the indeed non-trivial
situation with {,v}movq, where there are two load and two store
encodings available in 64-bit mode (when there's a memory
operand). I would expect to be able to control this as a
programmer, but I have no good idea on how to make this work.

Furthermore, and I'm sorry to say that, but something like
{disp32} was ill-advised altogether (just like the now deprecated
.d32): It's at best confusing for 16-bit addressing. This should
have been e.g. {dispw}. But that ship has sailed now.

Additionally - if .s is deprecated, why does the disassembler
continue to emit it?

Jan
H.J. Lu
2018-08-03 15:30:49 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
Post by Jan Beulich
And btw - it's nice to have all these pseudo prefixes, if only they
had actually worked half way correctly from the very beginning.
And I'm already leaving aside the case of the indeed non-trivial
situation with {,v}movq, where there are two load and two store
encodings available in 64-bit mode (when there's a memory
operand). I would expect to be able to control this as a
programmer, but I have no good idea on how to make this work.
Furthermore, and I'm sorry to say that, but something like
{disp32} was ill-advised altogether (just like the now deprecated
.d32): It's at best confusing for 16-bit addressing. This should
have been e.g. {dispw}. But that ship has sailed now.
Additionally - if .s is deprecated, why does the disassembler
continue to emit it?
A patch for disassembler is welcome.
--
H.J.
Jan Beulich
2018-08-03 15:50:55 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/

Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
behavior" in the sense that I might break anything that has
worked before. The perspective to take is that for the existing
test cases the behavior doesn't change. I'm sorry for not having
spelled it out this way before. I sincerely hope you don't mean
me to break again what I've just fixed, just to make sure the
behavior doesn't change _at all_.

Jan
H.J. Lu
2018-08-03 15:56:28 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
Post by Jan Beulich
behavior" in the sense that I might break anything that has
worked before. The perspective to take is that for the existing
test cases the behavior doesn't change. I'm sorry for not having
spelled it out this way before. I sincerely hope you don't mean
me to break again what I've just fixed, just to make sure the
behavior doesn't change _at all_.
--
H.J.
Jan Beulich
2018-08-03 16:07:45 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this

mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7

doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").

Jan
H.J. Lu
2018-08-03 16:14:14 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw

s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'

There is no need to fix these since the ".s" suffix has been deprecated.
--
H.J.
Jan Beulich
2018-08-06 06:29:06 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw
s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'
There is no need to fix these since the ".s" suffix has been deprecated.
"There is no need" can mean several things:
1) You want me to deliberately remove the code correction (which
may result in overall less readable / maintainable code).
2) You want me to simply not add tests for the corrected behavior
(which would be contrary to your general position that ideally any
code change would be accompanied by a test).
3) I can leave the patch the way it is, as it also doesn't mean the
behavior must not be fixed.
And perhaps more.

Based on what I've written before, I'm opposed to 1, I could live
with 2, but I'd much prefer 3.

A further note on deprecation of these suffixes: By looking at just
the source code, how did you expect me to know they're deprecated?
There was no comment whatsoever added to that effect back when
you've made that change, neither to the .c file nor to the respective
test cases (which, if you suggest to go with 2, should perhaps be
removed altogether).

Jan
H.J. Lu
2018-08-06 12:54:22 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw
s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'
There is no need to fix these since the ".s" suffix has been deprecated.
1) You want me to deliberately remove the code correction (which
may result in overall less readable / maintainable code).
2) You want me to simply not add tests for the corrected behavior
(which would be contrary to your general position that ideally any
code change would be accompanied by a test).
3) I can leave the patch the way it is, as it also doesn't mean the
behavior must not be fixed.
And perhaps more.
I don't want to make any changes to assembler, whose sole purposes
are to change/improve the behavior of the ".s" suffix.
Post by Jan Beulich
Based on what I've written before, I'm opposed to 1, I could live
with 2, but I'd much prefer 3.
A further note on deprecation of these suffixes: By looking at just
the source code, how did you expect me to know they're deprecated?
Can you recommend a good way to indicate that?
Post by Jan Beulich
There was no comment whatsoever added to that effect back when
you've made that change, neither to the .c file nor to the respective
test cases (which, if you suggest to go with 2, should perhaps be
removed altogether).
I have removed the ".s" suffix from the assembler manual, but kept
the testcases to avoid breaking existing codes. But we shouldn't
make further changes to improve it.
--
H.J.
Jan Beulich
2018-08-06 14:08:37 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw
s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'
There is no need to fix these since the ".s" suffix has been deprecated.
1) You want me to deliberately remove the code correction (which
may result in overall less readable / maintainable code).
2) You want me to simply not add tests for the corrected behavior
(which would be contrary to your general position that ideally any
code change would be accompanied by a test).
3) I can leave the patch the way it is, as it also doesn't mean the
behavior must not be fixed.
And perhaps more.
I don't want to make any changes to assembler, whose sole purposes
are to change/improve the behavior of the ".s" suffix.
Post by Jan Beulich
Based on what I've written before, I'm opposed to 1, I could live
with 2, but I'd much prefer 3.
A further note on deprecation of these suffixes: By looking at just
the source code, how did you expect me to know they're deprecated?
Can you recommend a good way to indicate that?
A code comment in the section responsible for the parsing of these
suffixes?
Post by H.J. Lu
Post by Jan Beulich
There was no comment whatsoever added to that effect back when
you've made that change, neither to the .c file nor to the respective
test cases (which, if you suggest to go with 2, should perhaps be
removed altogether).
I have removed the ".s" suffix from the assembler manual, but kept
the testcases to avoid breaking existing codes. But we shouldn't
make further changes to improve it.
But you realize that the fixing of .s is more a byproduct of fixing
{load} and {store}? That's why I keep saying that _not_ fixing
.s at the same time would likely result in worse (and hence harder
to maintain) code. And that's also why I'm considering option 2
above tolerable, albeit not ideal.

Jan
H.J. Lu
2018-08-06 15:09:49 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw
s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'
There is no need to fix these since the ".s" suffix has been deprecated.
1) You want me to deliberately remove the code correction (which
may result in overall less readable / maintainable code).
2) You want me to simply not add tests for the corrected behavior
(which would be contrary to your general position that ideally any
code change would be accompanied by a test).
3) I can leave the patch the way it is, as it also doesn't mean the
behavior must not be fixed.
And perhaps more.
I don't want to make any changes to assembler, whose sole purposes
are to change/improve the behavior of the ".s" suffix.
Post by Jan Beulich
Based on what I've written before, I'm opposed to 1, I could live
with 2, but I'd much prefer 3.
A further note on deprecation of these suffixes: By looking at just
the source code, how did you expect me to know they're deprecated?
Can you recommend a good way to indicate that?
A code comment in the section responsible for the parsing of these
suffixes?
Do you care enough to submit a patch?
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
There was no comment whatsoever added to that effect back when
you've made that change, neither to the .c file nor to the respective
test cases (which, if you suggest to go with 2, should perhaps be
removed altogether).
I have removed the ".s" suffix from the assembler manual, but kept
the testcases to avoid breaking existing codes. But we shouldn't
make further changes to improve it.
But you realize that the fixing of .s is more a byproduct of fixing
{load} and {store}? That's why I keep saying that _not_ fixing
.s at the same time would likely result in worse (and hence harder
to maintain) code. And that's also why I'm considering option 2
above tolerable, albeit not ideal.
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
--
H.J.
Jan Beulich
2018-08-06 15:59:29 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw
s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'
There is no need to fix these since the ".s" suffix has been deprecated.
1) You want me to deliberately remove the code correction (which
may result in overall less readable / maintainable code).
2) You want me to simply not add tests for the corrected behavior
(which would be contrary to your general position that ideally any
code change would be accompanied by a test).
3) I can leave the patch the way it is, as it also doesn't mean the
behavior must not be fixed.
And perhaps more.
I don't want to make any changes to assembler, whose sole purposes
are to change/improve the behavior of the ".s" suffix.
Post by Jan Beulich
Based on what I've written before, I'm opposed to 1, I could live
with 2, but I'd much prefer 3.
A further note on deprecation of these suffixes: By looking at just
the source code, how did you expect me to know they're deprecated?
Can you recommend a good way to indicate that?
A code comment in the section responsible for the parsing of these
suffixes?
Do you care enough to submit a patch?
I could do that, sure.
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
There was no comment whatsoever added to that effect back when
you've made that change, neither to the .c file nor to the respective
test cases (which, if you suggest to go with 2, should perhaps be
removed altogether).
I have removed the ".s" suffix from the assembler manual, but kept
the testcases to avoid breaking existing codes. But we shouldn't
make further changes to improve it.
But you realize that the fixing of .s is more a byproduct of fixing
{load} and {store}? That's why I keep saying that _not_ fixing
.s at the same time would likely result in worse (and hence harder
to maintain) code. And that's also why I'm considering option 2
above tolerable, albeit not ideal.
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.

Jan
H.J. Lu
2018-08-06 16:25:40 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Please don't make any changes to the deprecated ".s".
Excuse me, but how many more times should I state that I don't
make any changes to its behavior? I solely make {store} no longer
match .s in behavior. In fact I've specifically undone the change
to .s, in anticipation of your objection to any adjustment to it.
Why do you change testcases of the .s suffix?
s/change/add to/
Deprecated or no, I think the .s suffix should still work, including
not causing assembly to fail when used. Try assembling the
additions without the source adjustments, and I think you'll find
some will fail. To me such adjustments are not "changes to its
Which one?
The additions to *opts.s. For example, this
mov 0x12345678, %eax
mov.s 0x12345678, %eax
mov %eax, 0x12345678
mov.s %eax, 0x12345678
mov 0x123456789abcdef0, %eax
mov.s 0x123456789abcdef0, %eax
mov %eax, 0x123456789abcdef0
mov.s %eax, 0x123456789abcdef0
movabs 0x123456789abcdef0, %eax
movabs.s 0x123456789abcdef0, %eax
movabs %eax, 0x123456789abcdef0
movabs.s %eax, 0x123456789abcdef0
mov %eax, (%rdi)
mov.s %eax, (%rdi)
mov (%rdi), %eax
mov.s (%rdi), %eax
mov %cr0, %rax
mov.s %cr0, %rax
mov %rax, %cr7
mov.s %rax, %cr7
mov %dr0, %rax
mov.s %dr0, %rax
mov %rax, %dr7
mov.s %rax, %dr7
doesn't assemble with 2.31.1 (several "unsupported instruction"
and one "operand size mismatch").
I saw
s.s:4: Error: unsupported instruction `mov'
s.s:6: Error: unsupported instruction `mov'
s.s:10: Error: operand size mismatch for `movabs'
s.s:14: Error: unsupported instruction `mov'
s.s:18: Error: unsupported instruction `mov'
s.s:22: Error: unsupported instruction `mov'
There is no need to fix these since the ".s" suffix has been deprecated.
1) You want me to deliberately remove the code correction (which
may result in overall less readable / maintainable code).
2) You want me to simply not add tests for the corrected behavior
(which would be contrary to your general position that ideally any
code change would be accompanied by a test).
3) I can leave the patch the way it is, as it also doesn't mean the
behavior must not be fixed.
And perhaps more.
I don't want to make any changes to assembler, whose sole purposes
are to change/improve the behavior of the ".s" suffix.
Post by Jan Beulich
Based on what I've written before, I'm opposed to 1, I could live
with 2, but I'd much prefer 3.
A further note on deprecation of these suffixes: By looking at just
the source code, how did you expect me to know they're deprecated?
Can you recommend a good way to indicate that?
A code comment in the section responsible for the parsing of these
suffixes?
Do you care enough to submit a patch?
I could do that, sure.
Thank for doing that.
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
There was no comment whatsoever added to that effect back when
you've made that change, neither to the .c file nor to the respective
test cases (which, if you suggest to go with 2, should perhaps be
removed altogether).
I have removed the ".s" suffix from the assembler manual, but kept
the testcases to avoid breaking existing codes. But we shouldn't
make further changes to improve it.
But you realize that the fixing of .s is more a byproduct of fixing
{load} and {store}? That's why I keep saying that _not_ fixing
.s at the same time would likely result in worse (and hence harder
to maintain) code. And that's also why I'm considering option 2
above tolerable, albeit not ideal.
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
--
H.J.
Jan Beulich
2018-08-07 07:37:24 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).

Jan
H.J. Lu
2018-08-07 12:06:34 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).
Your change is't needed unless you can show that it improves {load}
or {store}.
--
H.J.
Jan Beulich
2018-08-07 13:13:24 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).
Your change is't needed unless you can show that it improves {load}
or {store}.
H.J., please. What is the purpose of me adding a whole lot of stuff
to *pseudos.s? Try assembling this without this patch in place. Then
comment out all the lines that cause errors, and look at the resulting
mess: {load} and {store} don't have their supposed meaning in
quite a few cases without this patch (in fact often the opposite
results). Hence the need to disconnect {store} from the (as you say
deprecated) .s suffix, so that .s can (mostly) remain as bogus as it
always was (just not producing as many errors anymore, which -
as said - is mostly a side effect of fixing the pseudo prefixes), while
{store} can be made act as its name says.

Jan
H.J. Lu
2018-08-07 13:40:23 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).
Your change is't needed unless you can show that it improves {load}
or {store}.
H.J., please. What is the purpose of me adding a whole lot of stuff
to *pseudos.s? Try assembling this without this patch in place. Then
1. Verify that your change has expected impact on {load} and {store}.
2. Make sure that their behavior is unchanged in the future.

It is perfectly OK for the ".s" suffix to fail since it has been deprecated.
--
H.J.
Jan Beulich
2018-08-07 14:18:10 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).
Your change is't needed unless you can show that it improves {load}
or {store}.
H.J., please. What is the purpose of me adding a whole lot of stuff
to *pseudos.s? Try assembling this without this patch in place. Then
1. Verify that your change has expected impact on {load} and {store}.
That's what the test case additions (*pseudos.s) are for.
Post by H.J. Lu
2. Make sure that their behavior is unchanged in the future.
Again - that's what the test case additions (*pseudos.s) are for.
Post by H.J. Lu
It is perfectly OK for the ".s" suffix to fail since it has been deprecated.
But it is then also (imo) perfectly okay if some previously broken
.s uses now suddenly work. And by extension it could then also
be okay to actually test that those now working cases work
sensibly (and will continue to work in the future).

In the end I _still_ don't know what you want me to do.

Jan
H.J. Lu
2018-08-07 14:49:30 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).
Your change is't needed unless you can show that it improves {load}
or {store}.
H.J., please. What is the purpose of me adding a whole lot of stuff
to *pseudos.s? Try assembling this without this patch in place. Then
1. Verify that your change has expected impact on {load} and {store}.
That's what the test case additions (*pseudos.s) are for.
The ".s" suffix tests != {load} and {store} tests.
Post by Jan Beulich
Post by H.J. Lu
2. Make sure that their behavior is unchanged in the future.
Again - that's what the test case additions (*pseudos.s) are for.
Post by H.J. Lu
It is perfectly OK for the ".s" suffix to fail since it has been deprecated.
But it is then also (imo) perfectly okay if some previously broken
.s uses now suddenly work. And by extension it could then also
be okay to actually test that those now working cases work
sensibly (and will continue to work in the future).
In the end I _still_ don't know what you want me to do.
I don't want any new ".s" suffix tests.
--
H.J.
Jan Beulich
2018-08-07 14:59:22 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
But there is no indication at all in your patch to show that it does
anything remotely to {load} nor {store}. All your testcase changes
are for the ".s" suffix.
There's a whole lot of stuff getting added to *pseudos.s.
That will make sure that {load} and {store} are handler properly
by actually testing them, instead of relying on the deprecated
".s" suffix.
I'm afraid I'm now confused by the "will" in your response: This
makes it sound as if you assume something is yet to be added. But
all those tests are already there. Bottom line - I'm still hanging in
the air as to which way to proceed (see the earlier enumerated
three options).
Your change is't needed unless you can show that it improves {load}
or {store}.
H.J., please. What is the purpose of me adding a whole lot of stuff
to *pseudos.s? Try assembling this without this patch in place. Then
1. Verify that your change has expected impact on {load} and {store}.
That's what the test case additions (*pseudos.s) are for.
The ".s" suffix tests != {load} and {store} tests.
Well, of course so far the patch adds both, which I did because
you basically always ask for test cases, and because I wasn't really
aware of the deprecation of .s.
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
2. Make sure that their behavior is unchanged in the future.
Again - that's what the test case additions (*pseudos.s) are for.
Post by H.J. Lu
It is perfectly OK for the ".s" suffix to fail since it has been deprecated.
But it is then also (imo) perfectly okay if some previously broken
.s uses now suddenly work. And by extension it could then also
be okay to actually test that those now working cases work
sensibly (and will continue to work in the future).
In the end I _still_ don't know what you want me to do.
I don't want any new ".s" suffix tests.
I'll get rid of them then.

Jan
Jan Beulich
2018-08-02 06:50:39 UTC
Permalink
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.

Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.

gas/
2018-08-02 Jan Beulich <***@suse.com>

* config/tc-i386.c (operand_size_match): Mirror
.reg/.regsimd/.acc handling from forward to reverse case.
(build_vex_prefix): Check first and last operand types are equal
and also consider .d for swapping operands for VEX2 encoding.
(match_template): Clear found_reverse_match on every iteration.
Use Opcode_SIMD_FloatD and Opcode_SIMD_IntD.
* testsuite/gas/i386/pseudos.s,
testsuite/gas/i386/x86-64-pseudos.s: Add kmov* tests.
* testsuite/gas/i386/pseudos.d,
testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations.

opcodes/
2018-08-02 Jan Beulich <***@suse.com>

* i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
Fold load and store templates where possible, adding D. Drop
IgnoreSize where it was pointlessly present. Drop redundant
*word.
* i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2032,11 +2032,18 @@ mismatch:

for (j = 0; j < 2; j++)
{
- if ((t->operand_types[j].bitfield.reg
- || t->operand_types[j].bitfield.acc)
+ if (t->operand_types[j].bitfield.reg
&& !match_operand_size (t, j, !j))
goto mismatch;

+ if (t->operand_types[j].bitfield.regsimd
+ && !match_simd_size (t, j, !j))
+ goto mismatch;
+
+ if (t->operand_types[j].bitfield.acc
+ && (!match_operand_size (t, j, !j) || !match_simd_size (t, j, !j)))
+ goto mismatch;
+
if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
goto mismatch;
}
@@ -3334,8 +3341,9 @@ build_vex_prefix (const insn_template *t
if (i.vec_encoding != vex_encoding_vex3
&& i.dir_encoding == dir_encoding_default
&& i.operands == i.reg_operands
+ && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
&& i.tm.opcode_modifier.vexopcode == VEX0F
- && i.tm.opcode_modifier.load
+ && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
&& i.rex == REX_B)
{
unsigned int xchg = i.operands - 1;
@@ -3356,8 +3364,11 @@ build_vex_prefix (const insn_template *t
i.rm.regmem = i.rm.reg;
i.rm.reg = xchg;

- /* Use the next insn. */
- i.tm = t[1];
+ if (i.tm.opcode_modifier.d)
+ i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
+ ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
+ else /* Use the next insn. */
+ i.tm = t[1];
}

if (i.tm.opcode_modifier.vex == VEXScalar)
@@ -5501,6 +5512,7 @@ match_template (char mnem_suffix)
for (t = current_templates->start; t < current_templates->end; t++)
{
addr_prefix_disp = -1;
+ found_reverse_match = 0;

if (i.operands != t->operands)
continue;
@@ -5751,6 +5763,13 @@ check_reverse:
found_reverse_match = 0;
else if (operand_types[0].bitfield.tbyte)
found_reverse_match = Opcode_FloatD;
+ else if (operand_types[0].bitfield.xmmword
+ || operand_types[1].bitfield.xmmword
+ || operand_types[0].bitfield.regmmx
+ || operand_types[1].bitfield.regmmx
+ || is_any_vex_encoding(t))
+ found_reverse_match = (t->base_opcode & 0xee) != 0x6e
+ ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
else
found_reverse_match = Opcode_D;
if (t->opcode_modifier.floatr)
@@ -5821,10 +5840,7 @@ check_reverse:
slip through to break. */
}
if (!found_cpu_match)
- {
- found_reverse_match = 0;
- continue;
- }
+ continue;

/* Check if vector and VEX operands are valid. */
if (check_VecOperands (t) || VEX_check_operands (t))
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -68,6 +68,26 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+[a-f0-9]+: 0f 21 c7 mov %db0,%edi
+[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+[a-f0-9]+: 11 07 adc %eax,\(%edi\)
+[a-f0-9]+: 13 07 adc \(%edi\),%eax
+[a-f0-9]+: 11 07 adc %eax,\(%edi\)
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -65,6 +65,26 @@ _start:
{load} mov %eax, %dr7
{store} mov %dr0, %edi
{store} mov %eax, %dr7
+ {load} kmovb %k0, %edi
+ {load} kmovb %eax, %k7
+ {store} kmovb %k0, %edi
+ {store} kmovb %eax, %k7
+ {load} kmovd %k0, %edi
+ {load} kmovd %eax, %k7
+ {store} kmovd %k0, %edi
+ {store} kmovd %eax, %k7
+ {load} kmovw %k0, %edi
+ {load} kmovw %eax, %k7
+ {store} kmovw %k0, %edi
+ {store} kmovw %eax, %k7
+ {load} kmovb %k0, %k7
+ {store} kmovb %k0, %k7
+ {load} kmovd %k0, %k7
+ {store} kmovd %k0, %k7
+ {load} kmovq %k0, %k7
+ {store} kmovq %k0, %k7
+ {load} kmovw %k0, %k7
+ {store} kmovw %k0, %k7
{load} adc %eax, (%edi)
{load} adc (%edi), %eax
{store} adc %eax, (%edi)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -76,6 +76,30 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+[a-f0-9]+: 0f 21 c7 mov %db0,%rdi
+[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c4 e1 fb 93 f8 kmovq %k0,%rdi
+ +[a-f0-9]+: c4 e1 fb 92 f8 kmovq %rax,%k7
+ +[a-f0-9]+: c4 e1 fb 93 f8 kmovq %k0,%rdi
+ +[a-f0-9]+: c4 e1 fb 92 f8 kmovq %rax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
+[a-f0-9]+: 13 07 adc \(%rdi\),%eax
+[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -73,6 +73,30 @@ _start:
{load} mov %rax, %dr7
{store} mov %dr0, %rdi
{store} mov %rax, %dr7
+ {load} kmovb %k0, %edi
+ {load} kmovb %eax, %k7
+ {store} kmovb %k0, %edi
+ {store} kmovb %eax, %k7
+ {load} kmovd %k0, %edi
+ {load} kmovd %eax, %k7
+ {store} kmovd %k0, %edi
+ {store} kmovd %eax, %k7
+ {load} kmovq %k0, %rdi
+ {load} kmovq %rax, %k7
+ {store} kmovq %k0, %rdi
+ {store} kmovq %rax, %k7
+ {load} kmovw %k0, %edi
+ {load} kmovw %eax, %k7
+ {store} kmovw %k0, %edi
+ {store} kmovw %eax, %k7
+ {load} kmovb %k0, %k7
+ {store} kmovb %k0, %k7
+ {load} kmovd %k0, %k7
+ {store} kmovd %k0, %k7
+ {load} kmovq %k0, %k7
+ {store} kmovq %k0, %k7
+ {load} kmovw %k0, %k7
+ {store} kmovw %k0, %k7
{load} adc %eax, (%rdi)
{load} adc (%rdi), %eax
{store} adc %eax, (%rdi)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -855,6 +855,8 @@ typedef struct insn_template
unset if Regmem --> Reg. */
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */

/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -941,18 +941,12 @@ emms, 0, 0xf77, None, 2, CpuMMX, No_bSuf
// copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's
// spec). AMD's spec, having been in existence for much longer, failed to
// recognize that and specified movd for 32- and 64-bit operations.
-movd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|Qword|BaseIndex, RegXMM }
-movd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
-movd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { RegXMM, Qword|Reg64|BaseIndex }
-movd, 2, 0x660f6e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex, RegXMM }
-movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-movd, 2, 0x660f7e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Reg64|Qword|BaseIndex }
-movd, 2, 0xf6e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegMMX }
-movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex, RegMMX }
-movd, 2, 0xf7e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg32|Dword|Unspecified|BaseIndex }
-movd, 2, 0xf7e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegMMX, Reg64|Qword|BaseIndex }
+movd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM }
+movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|BaseIndex, RegXMM }
+movd, 2, 0x660f6e, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
+movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|BaseIndex, RegXMM }
+movd, 2, 0xf6e, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegMMX }
+movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|BaseIndex, RegMMX }
// In the 64bit mode the short form mov immediate is redefined to have
// 64bit displacement value. We put the 64bit displacement first and
// we only mark constants larger than 32bit as Disp64.
@@ -962,16 +956,12 @@ movq, 2, 0xc6, 0x0, 1, Cpu64, W|Modrm|Si
movq, 2, 0xb0, None, 1, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
movq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Qword|Unspecified|BaseIndex, RegXMM }
-movq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { RegXMM, Reg64|Qword|Unspecified|BaseIndex }
+movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM }
movq, 2, 0xf30f7e, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM }
movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM }
-movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|Qword|BaseIndex, RegXMM }
-movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Unspecified|Qword|BaseIndex }
-movq, 2, 0xf6f, None, 2, CpuMMX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX }
-movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|RegMMX }
-movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|Qword|BaseIndex, RegMMX }
-movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegMMX, Reg64|Unspecified|Qword|BaseIndex }
+movq, 2, 0x660f6e, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
+movq, 2, 0xf6f, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX }
+movq, 2, 0xf6e, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX }
// The segment register moves accept Reg64 so that a segment register
// can be copied to a 64 bit register, and vice versa.
movq, 2, 0x8c, None, 1, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2|SReg3, Reg64|RegMem }
@@ -1217,22 +1207,18 @@ minps, 2, 0x5d, None, 1, CpuAVX, Modrm|V
minps, 2, 0xf5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
minss, 2, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movaps, 2, 0x28, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movaps, 2, 0xf28, None, 2, CpuSSE, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movaps, 2, 0xf29, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movaps, 2, 0x28, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movaps, 2, 0xf28, None, 2, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movhlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
movhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movhps, 2, 0x17, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movhps, 2, 0xf17, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movhps, 2, 0xf16, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movlhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movlps, 2, 0xf13, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movlps, 2, 0xf12, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
@@ -1240,16 +1226,11 @@ movntps, 2, 0xf2b, None, 2, CpuSSE, Modr
movntq, 2, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, Qword|Unspecified|BaseIndex }
movntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
movntdq, 2, 0x660fe7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
-movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|BaseIndex }
-movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM }
-movss, 2, 0xf310, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
-movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|RegMem }
-movss, 2, 0xf30f10, None, 2, CpuSSE, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM }
-movups, 2, 0x10, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movups, 2, 0xf10, None, 2, CpuSSE, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movups, 2, 0xf11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM }
+movss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|RegMem, RegXMM }
+movss, 2, 0xf30f10, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
+movups, 2, 0x10, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movups, 2, 0xf10, None, 2, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulss, 2, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -1399,18 +1380,14 @@ minpd, 2, 0x665d, None, 1, CpuAVX, Modrm
minpd, 2, 0x660f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
minsd, 2, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
minsd, 2, 0xf20f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movapd, 2, 0x6628, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movapd, 2, 0x660f28, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movapd, 2, 0x660f29, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movapd, 2, 0x6628, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movapd, 2, 0x660f28, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movhpd, 2, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movhpd, 2, 0x660f16, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movhpd, 2, 0x660f17, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movhpd, 2, 0x660f16, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movlpd, 2, 0x660f12, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movlpd, 2, 0x660f13, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movlpd, 2, 0x660f12, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
@@ -1418,16 +1395,11 @@ movntpd, 2, 0x660f2b, None, 2, CpuSSE2,
// Intel mode string move.
movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Unspecified|BaseIndex, Unspecified|BaseIndex|EsSeg }
-movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
-movsd, 2, 0xf210, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
-movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|Regmem }
-movsd, 2, 0xf20f10, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-movupd, 2, 0x6610, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movupd, 2, 0x660f10, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
+movsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Regmem, RegXMM }
+movsd, 2, 0xf20f10, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+movupd, 2, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movupd, 2, 0x660f10, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulsd, 2, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -1480,14 +1452,10 @@ cvttps2dq, 2, 0xf35b, None, 1, CpuAVX, M
cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
maskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
-movdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movdqa, 2, 0x660f6f, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqa, 2, 0x660f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movdqu, 2, 0xf36f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movdqa, 2, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movdqa, 2, 0x660f6f, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movdqu, 2, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX }
movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM }
pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -2037,25 +2005,19 @@ vminpd, 3, 0x665d, None, 1, CpuAVX, Modr
vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vmovapd, 2, 0x6628, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
-vmovaps, 2, 0x28, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
+vmovapd, 2, 0x6628, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vmovaps, 2, 0x28, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
// vmovd really shouldn't allow for 64bit operand (vmovq is the right
// mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated
// by Intel AVX spec). To avoid extra template in gcc x86 backend and
// support assembler for AMD64, we accept 64bit operand on vmovd so
// that we can use one template for both SSE and AVX instructions.
-vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, RegXMM }
-vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
-vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|RegMem }
+vmovd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
+vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|RegMem, RegXMM }
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
-vmovdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
-vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
+vmovdqa, 2, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vmovdqu, 2, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovhpd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vmovhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
@@ -2074,22 +2036,17 @@ vmovntpd, 2, 0x662b, None, 1, CpuAVX, Mo
vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Qword|Unspecified|BaseIndex, RegXMM }
-vmovq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Qword|Unspecified|BaseIndex }
-vmovsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
-vmovsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
+vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
+vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xf210, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
-vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
+vmovss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
vmovss, 3, 0xf310, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
-vmovupd, 2, 0x6610, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
-vmovups, 2, 0x10, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
+vmovupd, 2, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vmovups, 2, 0x10, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -2867,8 +2824,7 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|N

// MPX instructions.
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex, RegBND }
-bndmov, 2, 0x660f1a, None, 2, CpuMPX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
-bndmov, 2, 0x660f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|RegBND }
+bndmov, 2, 0x660f1a, None, 2, CpuMPX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND }
bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
@@ -2907,8 +2863,7 @@ kxorw, 3, 0x47, None, 1, CpuAVX512F, Mod

kmovw, 2, 0x90, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Word|Unspecified|BaseIndex, RegMask }
kmovw, 2, 0x91, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Word|Unspecified|BaseIndex }
-kmovw, 2, 0x92, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
-kmovw, 2, 0x93, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
+kmovw, 2, 0x92, None, 1, CpuAVX512F, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }

knotw, 2, 0x44, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
kortestw, 2, 0x98, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -3730,40 +3685,23 @@ vmaxss, 4, 0xF35F, None, 1, CpuAVX512F,
vminss, 3, 0xF35D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
vminss, 4, 0xF35D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }

-vmovapd, 2, 0x6628, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovapd, 2, 0x6629, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
+vmovapd, 2, 0x6628, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovntpd, 2, 0x662B, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
+vmovupd, 2, 0x6610, None, 1, CpuAVX512F, D|Modrm|Load|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

-vmovupd, 2, 0x6610, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovupd, 2, 0x6611, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovaps, 2, 0x28, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovaps, 2, 0x29, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
+vmovaps, 2, 0x28, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovntps, 2, 0x2B, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
+vmovups, 2, 0x10, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

-vmovups, 2, 0x10, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovups, 2, 0x11, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovd, 2, 0x666E, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x667E, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+vmovd, 2, 0x666E, None, 1, CpuAVX512F, D|Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }

vmovddup, 2, 0xF212, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM }

-vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqa64, 2, 0x667F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqa32, 2, 0x667F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
+vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovntdq, 2, 0x66E7, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
-
-vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu32, 2, 0xF37F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu64, 2, 0xF37F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
+vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

vmovhlps, 3, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovlhps, 3, 0x16, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
@@ -3778,22 +3716,19 @@ vmovhps, 2, 0x17, None, 1, CpuAVX512F, M
vmovlps, 3, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vmovlps, 2, 0x13, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }

-vmovq, 2, 0x666E, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Reg64, RegXMM }
-vmovq, 2, 0x667E, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Reg64 }
+vmovq, 2, 0x666E, None, 1, CpuAVX512F|Cpu64, D|Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovq, 2, 0xF37E, None, 1, CpuAVX512F, Load|Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovq, 2, 0x66D6, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

-vmovsd, 2, 0xF211, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+vmovsd, 2, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xF210, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovsd, 2, 0xF210, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xF211, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }

vmovshdup, 2, 0xF316, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovsldup, 2, 0xF312, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

-vmovss, 2, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
+vmovss, 2, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
vmovss, 3, 0xF310, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovss, 2, 0xF310, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
vmovss, 3, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }

vpabsd, 2, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -4214,6 +4149,7 @@ kandd, 3, 0x6641, None, 1, CpuAVX512BW,
kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
kmovd, 2, 0x6690, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex, RegMask }
kmovd, 2, 0x6691, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspecified|BaseIndex }
+kmovd, 2, 0xF292, None, 1, CpuAVX512BW, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
knotd, 2, 0x6644, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
kord, 3, 0x6645, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kortestd, 2, 0x6698, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -4226,6 +4162,7 @@ kandnq, 3, 0x42, None, 1, CpuAVX512BW, M
kandq, 3, 0x41, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kmovq, 2, 0x90, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex, RegMask }
kmovq, 2, 0x91, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecified|BaseIndex }
+kmovq, 2, 0xF292, None, 1, CpuAVX512BW, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask }
knotq, 2, 0x44, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
korq, 3, 0x45, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kortestq, 2, 0x98, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -4235,11 +4172,6 @@ kunpckwd, 3, 0x4B, None, 1, CpuAVX512BW,
kxnorq, 3, 0x46, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }

-kmovd, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
-kmovd, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
-kmovq, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask }
-kmovq, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg64 }
-
kshiftld, 3, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
kshiftlq, 3, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
kshiftrd, 3, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
@@ -4247,11 +4179,8 @@ kshiftrq, 3, 0x6631, None, 1, CpuAVX512B

vdbpsadbw, 4, 0x6642, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

-vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
+vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

vpabsb, 2, 0x661C, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vpmaxsb, 3, 0x663C, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
@@ -4418,8 +4347,7 @@ kandb, 3, 0x6641, None, 1, CpuAVX512DQ,
kandnb, 3, 0x6642, None, 1, CpuAVX512DQ, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kmovb, 2, 0x6690, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Byte|Unspecified|BaseIndex, RegMask }
kmovb, 2, 0x6691, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Byte|Unspecified|BaseIndex }
-kmovb, 2, 0x6692, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
-kmovb, 2, 0x6693, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
+kmovb, 2, 0x6692, None, 1, CpuAVX512DQ, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
knotb, 2, 0x6644, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
korb, 3, 0x6645, None, 1, CpuAVX512DQ, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kortestb, 2, 0x6698, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
H.J. Lu
2018-08-02 12:22:34 UTC
Permalink
Post by Jan Beulich
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.
Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
gas/
* config/tc-i386.c (operand_size_match): Mirror
.reg/.regsimd/.acc handling from forward to reverse case.
(build_vex_prefix): Check first and last operand types are equal
and also consider .d for swapping operands for VEX2 encoding.
(match_template): Clear found_reverse_match on every iteration.
Use Opcode_SIMD_FloatD and Opcode_SIMD_IntD.
* testsuite/gas/i386/pseudos.s,
testsuite/gas/i386/x86-64-pseudos.s: Add kmov* tests.
* testsuite/gas/i386/pseudos.d,
testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations.
opcodes/
* i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
Fold load and store templates where possible, adding D. Drop
IgnoreSize where it was pointlessly present. Drop redundant
*word.
* i386-tbl.h: Re-generate.
OK. Thanks.
--
H.J.
Jan Beulich
2018-08-02 06:51:19 UTC
Permalink
For now this is just for VMOVS{D,S}.

gas/
2018-08-02 Jan Beulich <***@suse.com>

* config/tc-i386.c (operand_size_match): Also deal with three
operand case.
(match_template): Also allow operand reversal for three operand
templates.

opcodes/
2018-08-02 Jan Beulich <***@suse.com>

* i386-opc.tbl (vmovsd, vmovss): Fold register form load and
store templates, adding D.
* i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2028,23 +2028,26 @@ mismatch:
}

/* Check reverse. */
- gas_assert (i.operands == 2);
+ gas_assert (i.operands >= 2 && i.operands <= 3);

- for (j = 0; j < 2; j++)
+ for (j = 0; j < i.operands; j++)
{
+ unsigned int given = i.operands - j - 1;
+
if (t->operand_types[j].bitfield.reg
- && !match_operand_size (t, j, !j))
+ && !match_operand_size (t, j, given))
goto mismatch;

if (t->operand_types[j].bitfield.regsimd
- && !match_simd_size (t, j, !j))
+ && !match_simd_size (t, j, given))
goto mismatch;

if (t->operand_types[j].bitfield.acc
- && (!match_operand_size (t, j, !j) || !match_simd_size (t, j, !j)))
+ && (!match_operand_size (t, j, given)
+ || !match_simd_size (t, j, given)))
goto mismatch;

- if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
+ if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
goto mismatch;
}

@@ -5685,6 +5688,9 @@ match_template (char mnem_suffix)
&& i.types[0].bitfield.acc
&& operand_type_check (i.types[1], anymem))
continue;
+ /* Fall through. */
+
+ case 3:
if (!(size_match & MATCH_STRAIGHT))
goto check_reverse;
/* Reverse direction of operands if swapping is possible in the first
@@ -5693,7 +5699,7 @@ match_template (char mnem_suffix)
- the store form is requested, and the template is a load form,
- the non-default (swapped) form is requested. */
overlap1 = operand_type_and (operand_types[0], operand_types[1]);
- if (t->opcode_modifier.d && i.reg_operands == 2
+ if (t->opcode_modifier.d && i.reg_operands == i.operands
&& !operand_type_all_zero (&overlap1))
switch (i.dir_encoding)
{
@@ -5715,9 +5721,6 @@ match_template (char mnem_suffix)
case dir_encoding_default:
break;
}
- /* Fall through. */
-
- case 3:
/* If we want store form, we skip the current load. */
if ((i.dir_encoding == dir_encoding_store
|| i.dir_encoding == dir_encoding_swap)
@@ -5744,14 +5747,14 @@ check_reverse:
if (!(size_match & MATCH_REVERSE))
continue;
/* Try reversing direction of operands. */
- overlap0 = operand_type_and (i.types[0], operand_types[1]);
- overlap1 = operand_type_and (i.types[1], operand_types[0]);
+ overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
+ overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
if (!operand_type_match (overlap0, i.types[0])
- || !operand_type_match (overlap1, i.types[1])
+ || !operand_type_match (overlap1, i.types[i.operands - 1])
|| (check_register
&& !operand_type_register_match (i.types[0],
- operand_types[1],
- i.types[1],
+ operand_types[i.operands - 1],
+ i.types[i.operands - 1],
operand_types[0])))
{
/* Does not match either direction. */
@@ -5764,9 +5767,9 @@ check_reverse:
else if (operand_types[0].bitfield.tbyte)
found_reverse_match = Opcode_FloatD;
else if (operand_types[0].bitfield.xmmword
- || operand_types[1].bitfield.xmmword
+ || operand_types[i.operands - 1].bitfield.xmmword
|| operand_types[0].bitfield.regmmx
- || operand_types[1].bitfield.regmmx
+ || operand_types[i.operands - 1].bitfield.regmmx
|| is_any_vex_encoding(t))
found_reverse_match = (t->base_opcode & 0xee) != 0x6e
? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
@@ -5964,8 +5967,8 @@ check_reverse:

i.tm.base_opcode ^= found_reverse_match;

- i.tm.operand_types[0] = operand_types[1];
- i.tm.operand_types[1] = operand_types[0];
+ i.tm.operand_types[0] = operand_types[i.operands - 1];
+ i.tm.operand_types[i.operands - 1] = operand_types[0];
}

return t;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2038,13 +2038,11 @@ vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|
vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-vmovsd, 3, 0xf210, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }
vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
-vmovss, 3, 0xf310, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovss, 3, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }
vmovupd, 2, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovups, 2, 0x10, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -3721,15 +3719,13 @@ vmovq, 2, 0xF37E, None, 1, CpuAVX512F, L
vmovq, 2, 0x66D6, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

vmovsd, 2, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-vmovsd, 3, 0xF210, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovsd, 3, 0xF211, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovsd, 3, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

vmovshdup, 2, 0xF316, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovsldup, 2, 0xF312, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

vmovss, 2, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
-vmovss, 3, 0xF310, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovss, 3, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovss, 3, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

vpabsd, 2, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vrcp14ps, 2, 0x664C, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
H.J. Lu
2018-08-02 12:25:07 UTC
Permalink
Post by Jan Beulich
For now this is just for VMOVS{D,S}.
gas/
* config/tc-i386.c (operand_size_match): Also deal with three
operand case.
(match_template): Also allow operand reversal for three operand
templates.
opcodes/
* i386-opc.tbl (vmovsd, vmovss): Fold register form load and
store templates, adding D.
* i386-tbl.h: Re-generate.
OK. Thanks.
--
H.J.
Jan Beulich
2018-08-02 06:52:15 UTC
Permalink
This allows to simplify the code in a number of places.

gas/
2018-08-02 Jan Beulich <***@suse.com>

* config/tc-i386.c (build_modrm_byte): Use RegIP and RegIZ.
(output_disp): Use RegIP.
(i386_addressing_mode): Drop/replace uses of RegEip/RegEiz.
(parse_real_register): Use RegIZ.
* config/tc-i386-intel.c (i386_intel_simplify_register): Use
RegIZ.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust expectations.

opcodes/
2018-08-02 Jan Beulich <***@suse.com>

* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
(RegIP, RegIZ): Define.
* i386-reg.tbl: Adjust comments.
(rip): Use Qword instead of BaseIndex. Use RegIP.
(eip): Use Dword instead of BaseIndex. Use RegIP.
(riz): Add Qword. Use RegIZ.
(eiz): Add Dword. Use RegIZ.
* i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -289,8 +289,7 @@ i386_intel_simplify_register (expression
&& (i386_regtab[reg_num].reg_type.bitfield.xmmword
|| i386_regtab[reg_num].reg_type.bitfield.ymmword
|| i386_regtab[reg_num].reg_type.bitfield.zmmword
- || i386_regtab[reg_num].reg_num == RegRiz
- || i386_regtab[reg_num].reg_num == RegEiz))
+ || i386_regtab[reg_num].reg_num == RegIZ))
intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7139,8 +7139,7 @@ build_modrm_byte (void)

if (i.tm.opcode_modifier.vecsib)
{
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
abort ();

i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
@@ -7211,8 +7210,7 @@ build_modrm_byte (void)
else if (!i.tm.opcode_modifier.vecsib)
{
/* !i.base_reg && i.index_reg */
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
@@ -7238,8 +7236,7 @@ build_modrm_byte (void)
}
}
/* RIP addressing for 64bit mode. */
- else if (i.base_reg->reg_num == RegRip ||
- i.base_reg->reg_num == RegEip)
+ else if (i.base_reg->reg_num == RegIP)
{
gas_assert (!i.tm.opcode_modifier.vecsib);
i.rm.regmem = NO_BASE_REGISTER;
@@ -7331,8 +7328,7 @@ build_modrm_byte (void)
}
else if (!i.tm.opcode_modifier.vecsib)
{
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
@@ -8178,8 +8174,7 @@ output_disp (fragS *insn_start_frag, off
{
fixP->fx_tcbit = i.rex != 0;
if (i.base_reg
- && (i.base_reg->reg_num == RegRip
- || i.base_reg->reg_num == RegEip))
+ && (i.base_reg->reg_num == RegIP))
fixP->fx_tcbit2 = 1;
}
else
@@ -9280,9 +9275,7 @@ i386_addressing_mode (void)

if (addr_reg)
{
- if (addr_reg->reg_num == RegEip
- || addr_reg->reg_num == RegEiz
- || addr_reg->reg_type.bitfield.dword)
+ if (addr_reg->reg_type.bitfield.dword)
addr_mode = CODE_32BIT;
else if (flag_code != CODE_64BIT
&& addr_reg->reg_type.bitfield.word)
@@ -9392,21 +9385,18 @@ bad_address:
{
/* 32-bit/64-bit checks. */
if ((i.base_reg
- && (addr_mode == CODE_64BIT
- ? !i.base_reg->reg_type.bitfield.qword
- : !i.base_reg->reg_type.bitfield.dword)
- && (i.index_reg
- || (i.base_reg->reg_num
- != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
+ && ((addr_mode == CODE_64BIT
+ ? !i.base_reg->reg_type.bitfield.qword
+ : !i.base_reg->reg_type.bitfield.dword)
+ || (i.index_reg && i.base_reg->reg_num == RegIP)
+ || i.base_reg->reg_num == RegIZ))
|| (i.index_reg
&& !i.index_reg->reg_type.bitfield.xmmword
&& !i.index_reg->reg_type.bitfield.ymmword
&& !i.index_reg->reg_type.bitfield.zmmword
&& ((addr_mode == CODE_64BIT
- ? !(i.index_reg->reg_type.bitfield.qword
- || i.index_reg->reg_num == RegRiz)
- : !(i.index_reg->reg_type.bitfield.dword
- || i.index_reg->reg_num == RegEiz))
+ ? !i.index_reg->reg_type.bitfield.qword
+ : !i.index_reg->reg_type.bitfield.dword)
|| !i.index_reg->reg_type.bitfield.baseindex)))
goto bad_address;

@@ -9415,7 +9405,7 @@ bad_address:
|| (current_templates->start->base_opcode & ~1) == 0x0f1a)
{
/* They cannot use RIP-relative addressing. */
- if (i.base_reg && i.base_reg->reg_num == RegRip)
+ if (i.base_reg && i.base_reg->reg_num == RegIP)
{
as_bad (_("`%s' cannot be used here"), operand_string);
return 0;
@@ -10475,8 +10465,7 @@ parse_real_register (char *reg_string, c
return (const reg_entry *) NULL;

/* Don't allow fake index register unless allow_index_reg isn't 0. */
- if (!allow_index_reg
- && (r->reg_num == RegEiz || r->reg_num == RegRiz))
+ if (!allow_index_reg && r->reg_num == RegIZ)
return (const reg_entry *) NULL;

/* Upper 16 vector registers are only available with VREX in 64bit
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
.*:12: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:15: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
@@ -23,16 +23,16 @@
.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:39: Warning: register scaling is being ignored here
.*:40: Error: `base\(%rip\)' cannot be used here
-.*:41: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:41: Error: .*
.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:46: Warning: register scaling is being ignored here
.*:47: Error: `base\(%rip\)' cannot be used here
-.*:48: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:48: Error: .*
.*:51: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:53: Error: `\[rip\]' cannot be used here
-.*:54: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:54: Error: .*
.*:55: Error: `\[rax\+rsp\]' is not a valid base/index expression
.*:58: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:59: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
@@ -54,13 +54,13 @@
.*:84: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:85: Warning: register scaling is being ignored here
.*:86: Error: `\[rip\+base\]' cannot be used here
-.*:87: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:87: Error: .*
.*:88: Error: `\[rax\+rsp\]' is not a valid base/index expression
.*:91: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:92: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:93: Warning: register scaling is being ignored here
.*:94: Error: `\[rip\+base\]' cannot be used here
-.*:95: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:95: Error: .*
.*:96: Error: `\[rax\+rsp\]' is not a valid base/index expression
GAS LISTING .*

@@ -77,10 +77,7 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
@@ -122,12 +119,12 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+09
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
- GAS LISTING .*
-
-
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0103
[ ]*[1-9][0-9]*[ ]+bndcn %ecx, %bnd1
+ GAS LISTING .*
+
+
[ ]*[1-9][0-9]*[ ]+bndcn %cx, %bnd1
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
@@ -141,9 +138,7 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]+47
[ ]*[1-9][0-9]*[ ]+bndstx %bnd3, base\(%rip\)
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B0D bndstx %bnd1, base\(%eip\)
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]+bndstx %bnd1, base\(%eip\)
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
@@ -156,9 +151,7 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]*B8
[ ]*[1-9][0-9]*[ ]*bndldx base\(%rip\), %bnd1
-[ ]*[1-9][0-9]*[ ]*\?\?\?\? 670F1A1D bndldx base\(%eip\), %bnd3
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]*bndldx base\(%eip\), %bnd3
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
@@ -168,10 +161,7 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0203
[ ]*[1-9][0-9]*[ ]*bndmk bnd3, \[rip\]
-[ ]*[1-9][0-9]*[ ]*\?\?\?\? 67F30F1B bndmk bnd2, \[eip\]
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-[ ]*[1-9][0-9]*[ ]*15000000
-[ ]*[1-9][0-9]*[ ]*00
+[ ]*[1-9][0-9]*[ ]*bndmk bnd2, \[eip\]
[ ]*[1-9][0-9]*[ ]+bndmk bnd2, \[rax\+rsp\]
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
@@ -182,9 +172,6 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0203
[ ]*[1-9][0-9]*[ ]+
- GAS LISTING .*
-
-
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+08
@@ -195,6 +182,9 @@ GAS LISTING .*
[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
+ GAS LISTING .*
+
+
[ ]*[1-9][0-9]*[ ]+08
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
@@ -234,17 +224,12 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]+B8
[ ]*[1-9][0-9]*[ ]+bndstx \[rip\+base\], bnd1
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B1D bndstx \[eip\+base\], bnd3
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]+bndstx \[eip\+base\], bnd3
[ ]*[1-9][0-9]*[ ]+bndstx \[rax\+rsp\], bnd3
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
- GAS LISTING .*
-
-
[ ]*[1-9][0-9]*[ ]+1803
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
@@ -254,8 +239,6 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]+C7
[ ]*[1-9][0-9]*[ ]+bndldx bnd1, \[rip\+base\]
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A1D bndldx bnd3, \[eip\+base\]
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[eip\+base\]
[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[rax\+rsp\]
#pass
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -897,11 +897,9 @@ typedef struct
#define RegRex64 0x2 /* Extended 8 bit register. */
#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP ((unsigned char ) ~0)
/* EIZ and RIZ are fake index registers. */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ (RegIP - 1)
/* FLAT is a fake segment register (Intel mode). */
#define RegFlat ((unsigned char) ~0)
signed char dw2_regnum[2];
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -283,14 +283,14 @@ bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
-// No type will make these registers rejected for all purposes except
+// No Reg will make these registers rejected for all purposes except
// for addressing. This saves creating one extra type for RIP/EIP.
-rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
-eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
-// No type will make these registers rejected for all purposes except
+rip, Qword, RegRex64, RegIP, Dw2Inval, 16
+eip, Dword, RegRex64, RegIP, 8, Dw2Inval
+// No Reg will make these registers rejected for all purposes except
// for addressing.
-riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
-eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
+riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
+eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
// fp regs.
st(0), FloatReg|Acc, 0, 0, 11, 33
st(1), FloatReg, 0, 1, 12, 34
H.J. Lu
2018-08-02 12:28:09 UTC
Permalink
Post by Jan Beulich
This allows to simplify the code in a number of places.
gas/
* config/tc-i386.c (build_modrm_byte): Use RegIP and RegIZ.
(output_disp): Use RegIP.
(i386_addressing_mode): Drop/replace uses of RegEip/RegEiz.
(parse_real_register): Use RegIZ.
* config/tc-i386-intel.c (i386_intel_simplify_register): Use
RegIZ.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust expectations.
opcodes/
* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
(RegIP, RegIZ): Define.
* i386-reg.tbl: Adjust comments.
(rip): Use Qword instead of BaseIndex. Use RegIP.
(eip): Use Dword instead of BaseIndex. Use RegIP.
(riz): Add Qword. Use RegIZ.
(eiz): Add Dword. Use RegIZ.
* i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -289,8 +289,7 @@ i386_intel_simplify_register (expression
&& (i386_regtab[reg_num].reg_type.bitfield.xmmword
|| i386_regtab[reg_num].reg_type.bitfield.ymmword
|| i386_regtab[reg_num].reg_type.bitfield.zmmword
- || i386_regtab[reg_num].reg_num == RegRiz
- || i386_regtab[reg_num].reg_num == RegEiz))
+ || i386_regtab[reg_num].reg_num == RegIZ))
intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7139,8 +7139,7 @@ build_modrm_byte (void)
if (i.tm.opcode_modifier.vecsib)
{
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
abort ();
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
@@ -7211,8 +7210,7 @@ build_modrm_byte (void)
else if (!i.tm.opcode_modifier.vecsib)
{
/* !i.base_reg && i.index_reg */
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
@@ -7238,8 +7236,7 @@ build_modrm_byte (void)
}
}
/* RIP addressing for 64bit mode. */
- else if (i.base_reg->reg_num == RegRip ||
- i.base_reg->reg_num == RegEip)
+ else if (i.base_reg->reg_num == RegIP)
{
gas_assert (!i.tm.opcode_modifier.vecsib);
i.rm.regmem = NO_BASE_REGISTER;
@@ -7331,8 +7328,7 @@ build_modrm_byte (void)
}
else if (!i.tm.opcode_modifier.vecsib)
{
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
@@ -8178,8 +8174,7 @@ output_disp (fragS *insn_start_frag, off
{
fixP->fx_tcbit = i.rex != 0;
if (i.base_reg
- && (i.base_reg->reg_num == RegRip
- || i.base_reg->reg_num == RegEip))
+ && (i.base_reg->reg_num == RegIP))
fixP->fx_tcbit2 = 1;
}
else
@@ -9280,9 +9275,7 @@ i386_addressing_mode (void)
if (addr_reg)
{
- if (addr_reg->reg_num == RegEip
- || addr_reg->reg_num == RegEiz
- || addr_reg->reg_type.bitfield.dword)
+ if (addr_reg->reg_type.bitfield.dword)
addr_mode = CODE_32BIT;
else if (flag_code != CODE_64BIT
&& addr_reg->reg_type.bitfield.word)
{
/* 32-bit/64-bit checks. */
if ((i.base_reg
- && (addr_mode == CODE_64BIT
- ? !i.base_reg->reg_type.bitfield.qword
- : !i.base_reg->reg_type.bitfield.dword)
- && (i.index_reg
- || (i.base_reg->reg_num
- != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
+ && ((addr_mode == CODE_64BIT
+ ? !i.base_reg->reg_type.bitfield.qword
+ : !i.base_reg->reg_type.bitfield.dword)
+ || (i.index_reg && i.base_reg->reg_num == RegIP)
+ || i.base_reg->reg_num == RegIZ))
|| (i.index_reg
&& !i.index_reg->reg_type.bitfield.xmmword
&& !i.index_reg->reg_type.bitfield.ymmword
&& !i.index_reg->reg_type.bitfield.zmmword
&& ((addr_mode == CODE_64BIT
- ? !(i.index_reg->reg_type.bitfield.qword
- || i.index_reg->reg_num == RegRiz)
- : !(i.index_reg->reg_type.bitfield.dword
- || i.index_reg->reg_num == RegEiz))
+ ? !i.index_reg->reg_type.bitfield.qword
+ : !i.index_reg->reg_type.bitfield.dword)
|| !i.index_reg->reg_type.bitfield.baseindex)))
goto bad_address;
|| (current_templates->start->base_opcode & ~1) == 0x0f1a)
{
/* They cannot use RIP-relative addressing. */
- if (i.base_reg && i.base_reg->reg_num == RegRip)
+ if (i.base_reg && i.base_reg->reg_num == RegIP)
{
as_bad (_("`%s' cannot be used here"), operand_string);
return 0;
@@ -10475,8 +10465,7 @@ parse_real_register (char *reg_string, c
return (const reg_entry *) NULL;
/* Don't allow fake index register unless allow_index_reg isn't 0. */
- if (!allow_index_reg
- && (r->reg_num == RegEiz || r->reg_num == RegRiz))
+ if (!allow_index_reg && r->reg_num == RegIZ)
return (const reg_entry *) NULL;
/* Upper 16 vector registers are only available with VREX in 64bit
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
--
H.J.
Jan Beulich
2018-08-02 12:43:21 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
Are you suggesting to special case the place the error message now
gets raised, just to get the wording the same as before? What's wrong
with it being either the previous one or the analogue to "`(%rip)'
cannot be used here", i.e. "`(%eip)' cannot be used here". When a
single statement is wrong in multiple possible ways, I don't think there
should be a requirement which of the issues the assembler reports, as
long as it reports exactly one (I find it odd enough that there are
cases where two errors get reported for a single statement, but I'll
get to that eventually as well).

Jan
H.J. Lu
2018-08-02 12:49:08 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
Are you suggesting to special case the place the error message now
gets raised, just to get the wording the same as before? What's wrong
with it being either the previous one or the analogue to "`(%rip)'
cannot be used here", i.e. "`(%eip)' cannot be used here". When a
single statement is wrong in multiple possible ways, I don't think there
should be a requirement which of the issues the assembler reports, as
long as it reports exactly one (I find it odd enough that there are
cases where two errors get reported for a single statement, but I'll
get to that eventually as well).
We get an error today:

[***@gnu-tools-1 tmp]$ cat x.s
bndmk (%eip), %bnd2
[***@gnu-tools-1 tmp]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
[***@gnu-tools-1 tmp]$

With your change, what do we get?
--
H.J.
Jan Beulich
2018-08-02 16:06:29 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
Are you suggesting to special case the place the error message now
gets raised, just to get the wording the same as before? What's wrong
with it being either the previous one or the analogue to "`(%rip)'
cannot be used here", i.e. "`(%eip)' cannot be used here". When a
single statement is wrong in multiple possible ways, I don't think there
should be a requirement which of the issues the assembler reports, as
long as it reports exactly one (I find it odd enough that there are
cases where two errors get reported for a single statement, but I'll
get to that eventually as well).
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here

Jan
H.J. Lu
2018-08-02 16:33:21 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
Are you suggesting to special case the place the error message now
gets raised, just to get the wording the same as before? What's wrong
with it being either the previous one or the analogue to "`(%rip)'
cannot be used here", i.e. "`(%eip)' cannot be used here". When a
single statement is wrong in multiple possible ways, I don't think there
should be a requirement which of the issues the assembler reports, as
long as it reports exactly one (I find it odd enough that there are
cases where two errors get reported for a single statement, but I'll
get to that eventually as well).
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1

Why is there no error message for bndmk (%eip), %bnd2"? Also

`(%eip)' cannot be used here

contains less info than

32-bit address isn't allowed in 64-bit MPX instructions
--
H.J.
Jan Beulich
2018-08-03 06:55:27 UTC
Permalink
Post by Jan Beulich
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
Are you suggesting to special case the place the error message now
gets raised, just to get the wording the same as before? What's wrong
with it being either the previous one or the analogue to "`(%rip)'
cannot be used here", i.e. "`(%eip)' cannot be used here". When a
single statement is wrong in multiple possible ways, I don't think there
should be a requirement which of the issues the assembler reports, as
long as it reports exactly one (I find it odd enough that there are
cases where two errors get reported for a single statement, but I'll
get to that eventually as well).
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
Why is there no error message for bndmk (%eip), %bnd2"? Also
Well, I've explained this already, but maybe the connection isn't
as obvious to you as I thought it would be: _Any_ errors appearing
in the listing are an indication of a problem, because it means the
assembler didn't simply bail after finding an error. In the case here
it is

if (i.tm.cpu_flags.bitfield.cpumpx)
{
if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
else if (flag_code != CODE_16BIT
? i.prefix[ADDR_PREFIX]
: i.mem_operands && !i.prefix[ADDR_PREFIX])
as_bad (_("16-bit address isn't allowed in MPX instructions"));
}

Note how there no "return" here. That's the very inconsistency I
did explain before (see the parenthesized statements in my second
most recent response, still visible in quoted context above), and
that I mean to get to fixing eventually.

Bottom line - an error disappearing from the listing should not be
considered a problem, but an improvement (the only alternative
view I could accept would be if _all_ errors appeared in the listing).
Post by Jan Beulich
`(%eip)' cannot be used here
contains less info than
32-bit address isn't allowed in 64-bit MPX instructions
Why that? Everyone ought to know that %eip is 32 bits. And once
again - it being wrong to use 32-bit _or_ IP-relative addressing,
there shouldn't be a requirement which of the two gets reported.
So in the end this change of error message is because the error
now comes from parse_operands(), in which case md_assemble()
bails rather than reaching the piece of quoted code above. I view
it as entirely unreasonable to complicate the code in
i386_index_check() just to be able to emit that other diagnostic.

Jan
H.J. Lu
2018-08-03 15:33:43 UTC
Permalink
Post by Jan Beulich
Post by Jan Beulich
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
Are you suggesting to special case the place the error message now
gets raised, just to get the wording the same as before? What's wrong
with it being either the previous one or the analogue to "`(%rip)'
cannot be used here", i.e. "`(%eip)' cannot be used here". When a
single statement is wrong in multiple possible ways, I don't think there
should be a requirement which of the issues the assembler reports, as
long as it reports exactly one (I find it odd enough that there are
cases where two errors get reported for a single statement, but I'll
get to that eventually as well).
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
Why is there no error message for bndmk (%eip), %bnd2"? Also
Well, I've explained this already, but maybe the connection isn't
as obvious to you as I thought it would be: _Any_ errors appearing
in the listing are an indication of a problem, because it means the
assembler didn't simply bail after finding an error. In the case here
it is
if (i.tm.cpu_flags.bitfield.cpumpx)
{
if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
else if (flag_code != CODE_16BIT
? i.prefix[ADDR_PREFIX]
: i.mem_operands && !i.prefix[ADDR_PREFIX])
as_bad (_("16-bit address isn't allowed in MPX instructions"));
}
Note how there no "return" here. That's the very inconsistency I
We can add a return here.
Post by Jan Beulich
did explain before (see the parenthesized statements in my second
most recent response, still visible in quoted context above), and
that I mean to get to fixing eventually.
Bottom line - an error disappearing from the listing should not be
considered a problem, but an improvement (the only alternative
view I could accept would be if _all_ errors appeared in the listing).
Post by Jan Beulich
`(%eip)' cannot be used here
contains less info than
32-bit address isn't allowed in 64-bit MPX instructions
Why that? Everyone ought to know that %eip is 32 bits. And once
again - it being wrong to use 32-bit _or_ IP-relative addressing,
there shouldn't be a requirement which of the two gets reported.
So in the end this change of error message is because the error
now comes from parse_operands(), in which case md_assemble()
bails rather than reaching the piece of quoted code above. I view
it as entirely unreasonable to complicate the code in
i386_index_check() just to be able to emit that other diagnostic.
We should have the same error for both %eip and %eax for MPX
in 64-bit mode.
--
H.J.
Jan Beulich
2018-08-03 16:01:00 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by Jan Beulich
Post by Jan Beulich
Post by H.J. Lu
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
Why is there no error message for bndmk (%eip), %bnd2"? Also
Well, I've explained this already, but maybe the connection isn't
as obvious to you as I thought it would be: _Any_ errors appearing
in the listing are an indication of a problem, because it means the
assembler didn't simply bail after finding an error. In the case here
it is
if (i.tm.cpu_flags.bitfield.cpumpx)
{
if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
else if (flag_code != CODE_16BIT
? i.prefix[ADDR_PREFIX]
: i.mem_operands && !i.prefix[ADDR_PREFIX])
as_bad (_("16-bit address isn't allowed in MPX instructions"));
}
Note how there no "return" here. That's the very inconsistency I
We can add a return here.
And that's my plan going forward, as said.
Post by H.J. Lu
Post by Jan Beulich
did explain before (see the parenthesized statements in my second
most recent response, still visible in quoted context above), and
that I mean to get to fixing eventually.
Bottom line - an error disappearing from the listing should not be
considered a problem, but an improvement (the only alternative
view I could accept would be if _all_ errors appeared in the listing).
Post by Jan Beulich
`(%eip)' cannot be used here
contains less info than
32-bit address isn't allowed in 64-bit MPX instructions
Why that? Everyone ought to know that %eip is 32 bits. And once
again - it being wrong to use 32-bit _or_ IP-relative addressing,
there shouldn't be a requirement which of the two gets reported.
So in the end this change of error message is because the error
now comes from parse_operands(), in which case md_assemble()
bails rather than reaching the piece of quoted code above. I view
it as entirely unreasonable to complicate the code in
i386_index_check() just to be able to emit that other diagnostic.
We should have the same error for both %eip and %eax for MPX
in 64-bit mode.
I'm sorry, but I'm not going to cripple the change just so that your
unreasonable requirement can be met. Let's take a different example:

add (%cr1), (%cr0)
add (,%xmm1), (,%xmm0)

Are you telling me it matters whether the assembler complains about
the first or second operand being wrong, or there being two memory
operands when just one is allowed? Once again - when there are
multiple things wrong for a single insn, there should be no expectation
whatsoever as to which of the possible error messages actually gets
emitted, as that's an implementation detail of the assembler. If you
disagree here, then I'm looking forward for a very good explanation
of your standpoint.

Jan
H.J. Lu
2018-08-03 16:17:04 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by Jan Beulich
Post by Jan Beulich
Post by H.J. Lu
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
Why is there no error message for bndmk (%eip), %bnd2"? Also
Well, I've explained this already, but maybe the connection isn't
as obvious to you as I thought it would be: _Any_ errors appearing
in the listing are an indication of a problem, because it means the
assembler didn't simply bail after finding an error. In the case here
it is
if (i.tm.cpu_flags.bitfield.cpumpx)
{
if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
else if (flag_code != CODE_16BIT
? i.prefix[ADDR_PREFIX]
: i.mem_operands && !i.prefix[ADDR_PREFIX])
as_bad (_("16-bit address isn't allowed in MPX instructions"));
}
Note how there no "return" here. That's the very inconsistency I
We can add a return here.
And that's my plan going forward, as said.
Post by H.J. Lu
Post by Jan Beulich
did explain before (see the parenthesized statements in my second
most recent response, still visible in quoted context above), and
that I mean to get to fixing eventually.
Bottom line - an error disappearing from the listing should not be
considered a problem, but an improvement (the only alternative
view I could accept would be if _all_ errors appeared in the listing).
Post by Jan Beulich
`(%eip)' cannot be used here
contains less info than
32-bit address isn't allowed in 64-bit MPX instructions
Why that? Everyone ought to know that %eip is 32 bits. And once
again - it being wrong to use 32-bit _or_ IP-relative addressing,
there shouldn't be a requirement which of the two gets reported.
So in the end this change of error message is because the error
now comes from parse_operands(), in which case md_assemble()
bails rather than reaching the piece of quoted code above. I view
it as entirely unreasonable to complicate the code in
i386_index_check() just to be able to emit that other diagnostic.
We should have the same error for both %eip and %eax for MPX
in 64-bit mode.
I'm sorry, but I'm not going to cripple the change just so that your
add (%cr1), (%cr0)
add (,%xmm1), (,%xmm0)
Are you telling me it matters whether the assembler complains about
the first or second operand being wrong, or there being two memory
operands when just one is allowed? Once again - when there are
multiple things wrong for a single insn, there should be no expectation
whatsoever as to which of the possible error messages actually gets
emitted, as that's an implementation detail of the assembler. If you
disagree here, then I'm looking forward for a very good explanation
of your standpoint.
The 0x67 prefix in MPX instructions is ignored. That is why there is

32-bit address isn't allowed in 64-bit MPX instructions

We should keep this message for "%eip".
--
H.J.
H.J. Lu
2018-08-05 15:36:31 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
Post by Jan Beulich
Post by Jan Beulich
Post by H.J. Lu
bndmk (%eip), %bnd2
x.s:1: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
With your change, what do we get?
`(%eip)' cannot be used here
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
Why is there no error message for bndmk (%eip), %bnd2"? Also
Well, I've explained this already, but maybe the connection isn't
as obvious to you as I thought it would be: _Any_ errors appearing
in the listing are an indication of a problem, because it means the
assembler didn't simply bail after finding an error. In the case here
it is
if (i.tm.cpu_flags.bitfield.cpumpx)
{
if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
else if (flag_code != CODE_16BIT
? i.prefix[ADDR_PREFIX]
: i.mem_operands && !i.prefix[ADDR_PREFIX])
as_bad (_("16-bit address isn't allowed in MPX instructions"));
}
Note how there no "return" here. That's the very inconsistency I
We can add a return here.
And that's my plan going forward, as said.
Post by H.J. Lu
Post by Jan Beulich
did explain before (see the parenthesized statements in my second
most recent response, still visible in quoted context above), and
that I mean to get to fixing eventually.
Bottom line - an error disappearing from the listing should not be
considered a problem, but an improvement (the only alternative
view I could accept would be if _all_ errors appeared in the listing).
Post by Jan Beulich
`(%eip)' cannot be used here
contains less info than
32-bit address isn't allowed in 64-bit MPX instructions
Why that? Everyone ought to know that %eip is 32 bits. And once
again - it being wrong to use 32-bit _or_ IP-relative addressing,
there shouldn't be a requirement which of the two gets reported.
So in the end this change of error message is because the error
now comes from parse_operands(), in which case md_assemble()
bails rather than reaching the piece of quoted code above. I view
it as entirely unreasonable to complicate the code in
i386_index_check() just to be able to emit that other diagnostic.
We should have the same error for both %eip and %eax for MPX
in 64-bit mode.
I'm sorry, but I'm not going to cripple the change just so that your
add (%cr1), (%cr0)
add (,%xmm1), (,%xmm0)
Are you telling me it matters whether the assembler complains about
the first or second operand being wrong, or there being two memory
operands when just one is allowed? Once again - when there are
multiple things wrong for a single insn, there should be no expectation
whatsoever as to which of the possible error messages actually gets
emitted, as that's an implementation detail of the assembler. If you
disagree here, then I'm looking forward for a very good explanation
of your standpoint.
The 0x67 prefix in MPX instructions is ignored. That is why there is
32-bit address isn't allowed in 64-bit MPX instructions
We should keep this message for "%eip".
I checked:

[***@gnu-tools-1 build-x86_64-linux]$ cat /tmp/y.s
bndmk (%rip), %bnd2
bndmk (%eip), %bnd2
[***@gnu-tools-1 build-x86_64-linux]$ gcc -c /tmp/y.s
/tmp/y.s: Assembler messages:
/tmp/y.s:1: Error: `(%rip)' cannot be used here
/tmp/y.s:2: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
[***@gnu-tools-1 build-x86_64-linux]$

Your change generates the same error as %rip. Your change is OK.
Sorry for the confusion.

Thanks.
--
H.J.
Jan Beulich
2018-09-05 11:47:46 UTC
Permalink
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64

Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.

Jan
Jan Beulich
2018-09-05 13:03:05 UTC
Permalink
gas/
2018-09-05 Jan Beulich <***@suse.com>

* config/tc-i386.c (parse_insn): Extend comment ahead of pseudo-
suffix handling.

--- master.orig/gas/config/tc-i386.c 2018-09-05 08:43:36.267091854 +0200
+++ master/gas/config/tc-i386.c 2018-09-05 11:54:07.932567283 +0200
@@ -4516,7 +4516,8 @@ parse_insn (char *line, char *mnemonic)

if (!current_templates)
{
- /* Check if we should swap operand or force 32bit displacement in
+ /* Deprecated functionality (new code should use pseudo-prefixes instead):
+ Check if we should swap operand or force 32bit displacement in
encoding. */
if (mnem_p - 2 == dot_p && dot_p[1] == 's')
i.dir_encoding = dir_encoding_store;
Jan Beulich
2018-09-05 13:03:34 UTC
Permalink
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.

The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.

gas/
2018-09-05 Jan Beulich <***@suse.com>

* config/tc-i386.c (dir_encoding_swap): New enumerator.
(parse_insn): Use it.
(match_template): Re-write reversal check.
* testsuite/gas/i386/pseudos.s: Add various move, ALU, and FPU
tests.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
* testsuite/gas/i386/pseudos.d,
testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -376,7 +376,8 @@ struct _i386_insn
{
dir_encoding_default = 0,
dir_encoding_load,
- dir_encoding_store
+ dir_encoding_store,
+ dir_encoding_swap
} dir_encoding;

/* Prefer 8bit or 32bit displacement in encoding. */
@@ -4520,7 +4521,7 @@ parse_insn (char *line, char *mnemonic)
Check if we should swap operand or force 32bit displacement in
encoding. */
if (mnem_p - 2 == dot_p && dot_p[1] == 's')
- i.dir_encoding = dir_encoding_store;
+ i.dir_encoding = dir_encoding_swap;
else if (mnem_p - 3 == dot_p
&& dot_p[1] == 'd'
&& dot_p[2] == '8')
@@ -5700,15 +5701,40 @@ match_template (char mnem_suffix)
continue;
if (!(size_match & MATCH_STRAIGHT))
goto check_reverse;
- /* If we want store form, we reverse direction of operands. */
- if (i.dir_encoding == dir_encoding_store
- && t->opcode_modifier.d)
- goto check_reverse;
+ /* Reverse direction of operands if swapping is possible in the first
+ place (operands need to be symmetric) and
+ - the load form is requested, and the template is a store form,
+ - the store form is requested, and the template is a load form,
+ - the non-default (swapped) form is requested. */
+ overlap1 = operand_type_and (operand_types[0], operand_types[1]);
+ if (t->opcode_modifier.d && i.reg_operands == 2
+ && !operand_type_all_zero (&overlap1))
+ switch (i.dir_encoding)
+ {
+ case dir_encoding_load:
+ if (operand_type_check (operand_types[i.operands - 1], anymem)
+ || operand_types[i.operands - 1].bitfield.regmem)
+ goto check_reverse;
+ break;
+
+ case dir_encoding_store:
+ if (!operand_type_check (operand_types[i.operands - 1], anymem)
+ && !operand_types[i.operands - 1].bitfield.regmem)
+ goto check_reverse;
+ break;
+
+ case dir_encoding_swap:
+ goto check_reverse;
+
+ case dir_encoding_default:
+ break;
+ }
/* Fall through. */

case 3:
/* If we want store form, we skip the current load. */
- if (i.dir_encoding == dir_encoding_store
+ if ((i.dir_encoding == dir_encoding_store
+ || i.dir_encoding == dir_encoding_swap)
&& i.mem_operands == 0
&& t->opcode_modifier.load)
continue;
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -22,8 +22,231 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 89 c8 mov %ecx,%eax
- +[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 8b c1 mov %ecx,%eax
+ +[a-f0-9]+: 89 c8 mov %ecx,%eax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 13 c1 adc %ecx,%eax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 03 c1 add %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 23 c1 and %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 3b c1 cmp %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 0b c1 or %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 1b c1 sbb %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 2b c1 sub %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: 33 c1 xor %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: a1 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: a3 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: a1 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: a3 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: 89 07 mov %eax,\(%edi\)
+ +[a-f0-9]+: 8b 07 mov \(%edi\),%eax
+ +[a-f0-9]+: 89 07 mov %eax,\(%edi\)
+ +[a-f0-9]+: 8b 07 mov \(%edi\),%eax
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%edi
+ +[a-f0-9]+: 0f 22 f8 mov %eax,%cr7
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%edi
+ +[a-f0-9]+: 0f 22 f8 mov %eax,%cr7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%edi
+ +[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%edi
+ +[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+ +[a-f0-9]+: 11 07 adc %eax,\(%edi\)
+ +[a-f0-9]+: 13 07 adc \(%edi\),%eax
+ +[a-f0-9]+: 11 07 adc %eax,\(%edi\)
+ +[a-f0-9]+: 13 07 adc \(%edi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%edi\)
+ +[a-f0-9]+: 03 07 add \(%edi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%edi\)
+ +[a-f0-9]+: 03 07 add \(%edi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%edi\)
+ +[a-f0-9]+: 23 07 and \(%edi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%edi\)
+ +[a-f0-9]+: 23 07 and \(%edi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%edi\)
+ +[a-f0-9]+: 3b 07 cmp \(%edi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%edi\)
+ +[a-f0-9]+: 3b 07 cmp \(%edi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%edi\)
+ +[a-f0-9]+: 0b 07 or \(%edi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%edi\)
+ +[a-f0-9]+: 0b 07 or \(%edi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%edi\)
+ +[a-f0-9]+: 1b 07 sbb \(%edi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%edi\)
+ +[a-f0-9]+: 1b 07 sbb \(%edi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%edi\)
+ +[a-f0-9]+: 2b 07 sub \(%edi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%edi\)
+ +[a-f0-9]+: 2b 07 sub \(%edi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%edi\)
+ +[a-f0-9]+: 33 07 xor \(%edi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%edi\)
+ +[a-f0-9]+: 33 07 xor \(%edi\),%eax
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 7f c7 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 29 c7 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 11 c7 movups %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 11 c7 movss %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 29 c7 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 11 c7 movupd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 11 c7 movsd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 7f c7 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7f c7 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f d6 c7 movq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 29 c7 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 29 c7 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 29 c7 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 11 c7 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 11 c7 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 11 c7 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 11 c7 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 11 c7 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 29 c7 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 29 c7 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 29 c7 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 11 c7 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 11 c7 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 11 c7 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 11 c7 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 11 c7 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 7f c7 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 7f c7 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 7f c7 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 7f c7 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 7f c7 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7f c7 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 7f c7 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 7f c7 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 7f c7 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 7f c7 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 7f c7 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7f c7 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
@@ -50,8 +273,8 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
+[a-f0-9]+: 89 c8 mov %ecx,%eax
- +[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 8b c1 mov %ecx,%eax
+ +[a-f0-9]+: 89 c8 mov %ecx,%eax
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -16,9 +16,239 @@ _start:
{disp32} vmovaps (%eax),%xmm2
{evex} {disp8} vmovaps (%eax),%xmm2
{evex} {disp32} vmovaps (%eax),%xmm2
+
mov %ecx, %eax
{load} mov %ecx, %eax
{store} mov %ecx, %eax
+ adc %ecx, %eax
+ {load} adc %ecx, %eax
+ {store} adc %ecx, %eax
+ add %ecx, %eax
+ {load} add %ecx, %eax
+ {store} add %ecx, %eax
+ and %ecx, %eax
+ {load} and %ecx, %eax
+ {store} and %ecx, %eax
+ cmp %ecx, %eax
+ {load} cmp %ecx, %eax
+ {store} cmp %ecx, %eax
+ or %ecx, %eax
+ {load} or %ecx, %eax
+ {store} or %ecx, %eax
+ sbb %ecx, %eax
+ {load} sbb %ecx, %eax
+ {store} sbb %ecx, %eax
+ sub %ecx, %eax
+ {load} sub %ecx, %eax
+ {store} sub %ecx, %eax
+ xor %ecx, %eax
+ {load} xor %ecx, %eax
+ {store} xor %ecx, %eax
+
+ {load} mov 0x12345678, %eax
+ {load} mov %eax, 0x12345678
+ {store} mov 0x12345678, %eax
+ {store} mov %eax, 0x12345678
+ {load} mov %eax, (%edi)
+ {load} mov (%edi), %eax
+ {store} mov %eax, (%edi)
+ {store} mov (%edi), %eax
+ {load} mov %es, %edi
+ {load} mov %eax, %gs
+ {store} mov %es, %edi
+ {store} mov %eax, %gs
+ {load} mov %cr0, %edi
+ {load} mov %eax, %cr7
+ {store} mov %cr0, %edi
+ {store} mov %eax, %cr7
+ {load} mov %dr0, %edi
+ {load} mov %eax, %dr7
+ {store} mov %dr0, %edi
+ {store} mov %eax, %dr7
+ {load} adc %eax, (%edi)
+ {load} adc (%edi), %eax
+ {store} adc %eax, (%edi)
+ {store} adc (%edi), %eax
+ {load} add %eax, (%edi)
+ {load} add (%edi), %eax
+ {store} add %eax, (%edi)
+ {store} add (%edi), %eax
+ {load} and %eax, (%edi)
+ {load} and (%edi), %eax
+ {store} and %eax, (%edi)
+ {store} and (%edi), %eax
+ {load} cmp %eax, (%edi)
+ {load} cmp (%edi), %eax
+ {store} cmp %eax, (%edi)
+ {store} cmp (%edi), %eax
+ {load} or %eax, (%edi)
+ {load} or (%edi), %eax
+ {store} or %eax, (%edi)
+ {store} or (%edi), %eax
+ {load} sbb %eax, (%edi)
+ {load} sbb (%edi), %eax
+ {store} sbb %eax, (%edi)
+ {store} sbb (%edi), %eax
+ {load} sub %eax, (%edi)
+ {load} sub (%edi), %eax
+ {store} sub %eax, (%edi)
+ {store} sub (%edi), %eax
+ {load} xor %eax, (%edi)
+ {load} xor (%edi), %eax
+ {store} xor %eax, (%edi)
+ {store} xor (%edi), %eax
+
+ fadd %st, %st
+ {load} fadd %st, %st
+ {store} fadd %st, %st
+ fdiv %st, %st
+ {load} fdiv %st, %st
+ {store} fdiv %st, %st
+ fdivr %st, %st
+ {load} fdivr %st, %st
+ {store} fdivr %st, %st
+ fmul %st, %st
+ {load} fmul %st, %st
+ {store} fmul %st, %st
+ fsub %st, %st
+ {load} fsub %st, %st
+ {store} fsub %st, %st
+ fsubr %st, %st
+ {load} fsubr %st, %st
+ {store} fsubr %st, %st
+
+ movq %mm0, %mm7
+ {load} movq %mm0, %mm7
+ {store} movq %mm0, %mm7
+
+ movaps %xmm0, %xmm7
+ {load} movaps %xmm0, %xmm7
+ {store} movaps %xmm0, %xmm7
+ movups %xmm0, %xmm7
+ {load} movups %xmm0, %xmm7
+ {store} movups %xmm0, %xmm7
+ movss %xmm0, %xmm7
+ {load} movss %xmm0, %xmm7
+ {store} movss %xmm0, %xmm7
+ movapd %xmm0, %xmm7
+ {load} movapd %xmm0, %xmm7
+ {store} movapd %xmm0, %xmm7
+ movupd %xmm0, %xmm7
+ {load} movupd %xmm0, %xmm7
+ {store} movupd %xmm0, %xmm7
+ movsd %xmm0, %xmm7
+ {load} movsd %xmm0, %xmm7
+ {store} movsd %xmm0, %xmm7
+ movdqa %xmm0, %xmm7
+ {load} movdqa %xmm0, %xmm7
+ {store} movdqa %xmm0, %xmm7
+ movdqu %xmm0, %xmm7
+ {load} movdqu %xmm0, %xmm7
+ {store} movdqu %xmm0, %xmm7
+ movq %xmm0, %xmm7
+ {load} movq %xmm0, %xmm7
+ {store} movq %xmm0, %xmm7
+ vmovaps %xmm0, %xmm7
+ {load} vmovaps %xmm0, %xmm7
+ {store} vmovaps %xmm0, %xmm7
+ vmovaps %zmm0, %zmm7
+ {load} vmovaps %zmm0, %zmm7
+ {store} vmovaps %zmm0, %zmm7
+ vmovaps %xmm0, %xmm7{%k7}
+ {load} vmovaps %xmm0, %xmm7{%k7}
+ {store} vmovaps %xmm0, %xmm7{%k7}
+ vmovups %zmm0, %zmm7
+ {load} vmovups %zmm0, %zmm7
+ {store} vmovups %zmm0, %zmm7
+ vmovups %xmm0, %xmm7
+ {load} vmovups %xmm0, %xmm7
+ {store} vmovups %xmm0, %xmm7
+ vmovups %xmm0, %xmm7{%k7}
+ {load} vmovups %xmm0, %xmm7{%k7}
+ {store} vmovups %xmm0, %xmm7{%k7}
+ vmovss %xmm0, %xmm1, %xmm7
+ {load} vmovss %xmm0, %xmm1, %xmm7
+ {store} vmovss %xmm0, %xmm1, %xmm7
+ vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ vmovapd %xmm0, %xmm7
+ {load} vmovapd %xmm0, %xmm7
+ {store} vmovapd %xmm0, %xmm7
+ vmovapd %zmm0, %zmm7
+ {load} vmovapd %zmm0, %zmm7
+ {store} vmovapd %zmm0, %zmm7
+ vmovapd %xmm0, %xmm7{%k7}
+ {load} vmovapd %xmm0, %xmm7{%k7}
+ {store} vmovapd %xmm0, %xmm7{%k7}
+ vmovupd %xmm0, %xmm7
+ {load} vmovupd %xmm0, %xmm7
+ {store} vmovupd %xmm0, %xmm7
+ vmovupd %zmm0, %zmm7
+ {load} vmovupd %zmm0, %zmm7
+ {store} vmovupd %zmm0, %zmm7
+ vmovupd %xmm0, %xmm7{%k7}
+ {load} vmovupd %xmm0, %xmm7{%k7}
+ {store} vmovupd %xmm0, %xmm7{%k7}
+ vmovsd %xmm0, %xmm1, %xmm7
+ {load} vmovsd %xmm0, %xmm1, %xmm7
+ {store} vmovsd %xmm0, %xmm1, %xmm7
+ vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ vmovdqa %xmm0, %xmm7
+ {load} vmovdqa %xmm0, %xmm7
+ {store} vmovdqa %xmm0, %xmm7
+ vmovdqa32 %zmm0, %zmm7
+ {load} vmovdqa32 %zmm0, %zmm7
+ {store} vmovdqa32 %zmm0, %zmm7
+ vmovdqa32 %xmm0, %xmm7
+ {load} vmovdqa32 %xmm0, %xmm7
+ {store} vmovdqa32 %xmm0, %xmm7
+ vmovdqa64 %zmm0, %zmm7
+ {load} vmovdqa64 %zmm0, %zmm7
+ {store} vmovdqa64 %zmm0, %zmm7
+ vmovdqa64 %xmm0, %xmm7
+ {load} vmovdqa64 %xmm0, %xmm7
+ {store} vmovdqa64 %xmm0, %xmm7
+ vmovdqu %xmm0, %xmm7
+ {load} vmovdqu %xmm0, %xmm7
+ {store} vmovdqu %xmm0, %xmm7
+ vmovdqu8 %zmm0, %zmm7
+ {load} vmovdqu8 %zmm0, %zmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu8 %xmm0, %xmm7
+ {load} vmovdqu8 %xmm0, %xmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu16 %zmm0, %zmm7
+ {load} vmovdqu16 %zmm0, %zmm7
+ {store} vmovdqu16 %zmm0, %zmm7
+ vmovdqu16 %xmm0, %xmm7
+ {load} vmovdqu16 %xmm0, %xmm7
+ {store} vmovdqu16 %xmm0, %xmm7
+ vmovdqu32 %zmm0, %zmm7
+ {load} vmovdqu32 %zmm0, %zmm7
+ {store} vmovdqu32 %zmm0, %zmm7
+ vmovdqu32 %xmm0, %xmm7
+ {load} vmovdqu32 %xmm0, %xmm7
+ {store} vmovdqu32 %xmm0, %xmm7
+ vmovdqu64 %zmm0, %zmm7
+ {load} vmovdqu64 %zmm0, %zmm7
+ {store} vmovdqu64 %zmm0, %zmm7
+ vmovdqu64 %xmm0, %xmm7
+ {load} vmovdqu64 %xmm0, %xmm7
+ {store} vmovdqu64 %xmm0, %xmm7
+ vmovq %xmm0, %xmm7
+ {load} vmovq %xmm0, %xmm7
+ {store} vmovq %xmm0, %xmm7
+ {evex} vmovq %xmm0, %xmm7
+ {load} {evex} vmovq %xmm0, %xmm7
+ {store} {evex} vmovq %xmm0, %xmm7
+
+ bndmov %bnd3, %bnd0
+ {load} bndmov %bnd3, %bnd0
+ {store} bndmov %bnd3, %bnd0
+
movaps (%eax),%xmm2
{load} movaps (%eax),%xmm2
{store} movaps (%eax),%xmm2
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -22,8 +22,239 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 48 89 c8 mov %rcx,%rax
- +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+[a-f0-9]+: 48 8b c1 mov %rcx,%rax
+ +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 13 c1 adc %ecx,%eax
+ +[a-f0-9]+: 11 c8 adc %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 03 c1 add %ecx,%eax
+ +[a-f0-9]+: 01 c8 add %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 23 c1 and %ecx,%eax
+ +[a-f0-9]+: 21 c8 and %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 3b c1 cmp %ecx,%eax
+ +[a-f0-9]+: 39 c8 cmp %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 0b c1 or %ecx,%eax
+ +[a-f0-9]+: 09 c8 or %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 1b c1 sbb %ecx,%eax
+ +[a-f0-9]+: 19 c8 sbb %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 2b c1 sub %ecx,%eax
+ +[a-f0-9]+: 29 c8 sub %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: 33 c1 xor %ecx,%eax
+ +[a-f0-9]+: 31 c8 xor %ecx,%eax
+ +[a-f0-9]+: 8b 04 25 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: 89 04 25 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: 8b 04 25 78 56 34 12 mov 0x12345678,%eax
+ +[a-f0-9]+: 89 04 25 78 56 34 12 mov %eax,0x12345678
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs 0x123456789abcdef0,%eax
+ +[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs %eax,0x123456789abcdef0
+ +[a-f0-9]+: 89 07 mov %eax,\(%rdi\)
+ +[a-f0-9]+: 8b 07 mov \(%rdi\),%eax
+ +[a-f0-9]+: 89 07 mov %eax,\(%rdi\)
+ +[a-f0-9]+: 8b 07 mov \(%rdi\),%eax
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 8c c7 mov %es,%edi
+ +[a-f0-9]+: 8e e8 mov %eax,%gs
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%rdi
+ +[a-f0-9]+: 0f 22 f8 mov %rax,%cr7
+ +[a-f0-9]+: 0f 20 c7 mov %cr0,%rdi
+ +[a-f0-9]+: 0f 22 f8 mov %rax,%cr7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%rdi
+ +[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+ +[a-f0-9]+: 0f 21 c7 mov %db0,%rdi
+ +[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+ +[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
+ +[a-f0-9]+: 13 07 adc \(%rdi\),%eax
+ +[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
+ +[a-f0-9]+: 13 07 adc \(%rdi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%rdi\)
+ +[a-f0-9]+: 03 07 add \(%rdi\),%eax
+ +[a-f0-9]+: 01 07 add %eax,\(%rdi\)
+ +[a-f0-9]+: 03 07 add \(%rdi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%rdi\)
+ +[a-f0-9]+: 23 07 and \(%rdi\),%eax
+ +[a-f0-9]+: 21 07 and %eax,\(%rdi\)
+ +[a-f0-9]+: 23 07 and \(%rdi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%rdi\)
+ +[a-f0-9]+: 3b 07 cmp \(%rdi\),%eax
+ +[a-f0-9]+: 39 07 cmp %eax,\(%rdi\)
+ +[a-f0-9]+: 3b 07 cmp \(%rdi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%rdi\)
+ +[a-f0-9]+: 0b 07 or \(%rdi\),%eax
+ +[a-f0-9]+: 09 07 or %eax,\(%rdi\)
+ +[a-f0-9]+: 0b 07 or \(%rdi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%rdi\)
+ +[a-f0-9]+: 1b 07 sbb \(%rdi\),%eax
+ +[a-f0-9]+: 19 07 sbb %eax,\(%rdi\)
+ +[a-f0-9]+: 1b 07 sbb \(%rdi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%rdi\)
+ +[a-f0-9]+: 2b 07 sub \(%rdi\),%eax
+ +[a-f0-9]+: 29 07 sub %eax,\(%rdi\)
+ +[a-f0-9]+: 2b 07 sub \(%rdi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%rdi\)
+ +[a-f0-9]+: 33 07 xor \(%rdi\),%eax
+ +[a-f0-9]+: 31 07 xor %eax,\(%rdi\)
+ +[a-f0-9]+: 33 07 xor \(%rdi\),%eax
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+ +[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+ +[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+ +[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+ +[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+ +[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+ +[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 7f c7 movq %mm0,%mm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 29 c7 movaps %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
+ +[a-f0-9]+: 0f 11 c7 movups %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 11 c7 movss %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 29 c7 movapd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 11 c7 movupd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
+ +[a-f0-9]+: f2 0f 11 c7 movsd %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 7f c7 movdqa %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7f c7 movdqu %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f d6 c7 movq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 29 c7 vmovaps %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 29 c7 vmovaps %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 29 c7 vmovaps %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7c 48 11 c7 vmovups %zmm0,%zmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: c5 f8 11 c7 vmovups %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 7c 0f 11 c7 vmovups %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f2 11 c7 vmovss %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 76 0f 11 c7 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 29 c7 vmovapd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 29 c7 vmovapd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 29 c7 vmovapd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 11 c7 vmovupd %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 11 c7 vmovupd %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 fd 0f 11 c7 vmovupd %xmm0,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: c5 f3 11 c7 vmovsd %xmm0,%xmm1,%xmm7
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: 62 f1 f7 0f 11 c7 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 7f c7 vmovdqa %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 48 7f c7 vmovdqa32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7d 08 7f c7 vmovdqa32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 48 7f c7 vmovdqa64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 7f c7 vmovdqa64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7f c7 vmovdqu %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 48 7f c7 vmovdqu16 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 ff 08 7f c7 vmovdqu16 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 48 7f c7 vmovdqu32 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 7e 08 7f c7 vmovdqu32 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 48 7f c7 vmovdqu64 %zmm0,%zmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7f c7 vmovdqu64 %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
+ +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
@@ -63,8 +294,8 @@ Disassembly of section .text:
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
+[a-f0-9]+: 48 89 c8 mov %rcx,%rax
- +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+[a-f0-9]+: 48 8b c1 mov %rcx,%rax
+ +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
+[a-f0-9]+: 0f 28 10 movaps \(%rax\),%xmm2
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -16,9 +16,247 @@ _start:
{disp32} vmovaps (%rax),%xmm2
{evex} {disp8} vmovaps (%rax),%xmm2
{evex} {disp32} vmovaps (%rax),%xmm2
+
mov %rcx, %rax
{load} mov %rcx, %rax
{store} mov %rcx, %rax
+ adc %ecx, %eax
+ {load} adc %ecx, %eax
+ {store} adc %ecx, %eax
+ add %ecx, %eax
+ {load} add %ecx, %eax
+ {store} add %ecx, %eax
+ and %ecx, %eax
+ {load} and %ecx, %eax
+ {store} and %ecx, %eax
+ cmp %ecx, %eax
+ {load} cmp %ecx, %eax
+ {store} cmp %ecx, %eax
+ or %ecx, %eax
+ {load} or %ecx, %eax
+ {store} or %ecx, %eax
+ sbb %ecx, %eax
+ {load} sbb %ecx, %eax
+ {store} sbb %ecx, %eax
+ sub %ecx, %eax
+ {load} sub %ecx, %eax
+ {store} sub %ecx, %eax
+ xor %ecx, %eax
+ {load} xor %ecx, %eax
+ {store} xor %ecx, %eax
+
+ {load} mov 0x12345678, %eax
+ {load} mov %eax, 0x12345678
+ {store} mov 0x12345678, %eax
+ {store} mov %eax, 0x12345678
+ {load} mov 0x123456789abcdef0, %eax
+ {load} mov %eax, 0x123456789abcdef0
+ {store} mov 0x123456789abcdef0, %eax
+ {store} mov %eax, 0x123456789abcdef0
+ {load} movabs 0x123456789abcdef0, %eax
+ {load} movabs %eax, 0x123456789abcdef0
+ {store} movabs 0x123456789abcdef0, %eax
+ {store} movabs %eax, 0x123456789abcdef0
+ {load} mov %eax, (%rdi)
+ {load} mov (%rdi), %eax
+ {store} mov %eax, (%rdi)
+ {store} mov (%rdi), %eax
+ {load} mov %es, %edi
+ {load} mov %eax, %gs
+ {store} mov %es, %edi
+ {store} mov %eax, %gs
+ {load} mov %cr0, %rdi
+ {load} mov %rax, %cr7
+ {store} mov %cr0, %rdi
+ {store} mov %rax, %cr7
+ {load} mov %dr0, %rdi
+ {load} mov %rax, %dr7
+ {store} mov %dr0, %rdi
+ {store} mov %rax, %dr7
+ {load} adc %eax, (%rdi)
+ {load} adc (%rdi), %eax
+ {store} adc %eax, (%rdi)
+ {store} adc (%rdi), %eax
+ {load} add %eax, (%rdi)
+ {load} add (%rdi), %eax
+ {store} add %eax, (%rdi)
+ {store} add (%rdi), %eax
+ {load} and %eax, (%rdi)
+ {load} and (%rdi), %eax
+ {store} and %eax, (%rdi)
+ {store} and (%rdi), %eax
+ {load} cmp %eax, (%rdi)
+ {load} cmp (%rdi), %eax
+ {store} cmp %eax, (%rdi)
+ {store} cmp (%rdi), %eax
+ {load} or %eax, (%rdi)
+ {load} or (%rdi), %eax
+ {store} or %eax, (%rdi)
+ {store} or (%rdi), %eax
+ {load} sbb %eax, (%rdi)
+ {load} sbb (%rdi), %eax
+ {store} sbb %eax, (%rdi)
+ {store} sbb (%rdi), %eax
+ {load} sub %eax, (%rdi)
+ {load} sub (%rdi), %eax
+ {store} sub %eax, (%rdi)
+ {store} sub (%rdi), %eax
+ {load} xor %eax, (%rdi)
+ {load} xor (%rdi), %eax
+ {store} xor %eax, (%rdi)
+ {store} xor (%rdi), %eax
+
+ fadd %st, %st
+ {load} fadd %st, %st
+ {store} fadd %st, %st
+ fdiv %st, %st
+ {load} fdiv %st, %st
+ {store} fdiv %st, %st
+ fdivr %st, %st
+ {load} fdivr %st, %st
+ {store} fdivr %st, %st
+ fmul %st, %st
+ {load} fmul %st, %st
+ {store} fmul %st, %st
+ fsub %st, %st
+ {load} fsub %st, %st
+ {store} fsub %st, %st
+ fsubr %st, %st
+ {load} fsubr %st, %st
+ {store} fsubr %st, %st
+
+ movq %mm0, %mm7
+ {load} movq %mm0, %mm7
+ {store} movq %mm0, %mm7
+
+ movaps %xmm0, %xmm7
+ {load} movaps %xmm0, %xmm7
+ {store} movaps %xmm0, %xmm7
+ movups %xmm0, %xmm7
+ {load} movups %xmm0, %xmm7
+ {store} movups %xmm0, %xmm7
+ movss %xmm0, %xmm7
+ {load} movss %xmm0, %xmm7
+ {store} movss %xmm0, %xmm7
+ movapd %xmm0, %xmm7
+ {load} movapd %xmm0, %xmm7
+ {store} movapd %xmm0, %xmm7
+ movupd %xmm0, %xmm7
+ {load} movupd %xmm0, %xmm7
+ {store} movupd %xmm0, %xmm7
+ movsd %xmm0, %xmm7
+ {load} movsd %xmm0, %xmm7
+ {store} movsd %xmm0, %xmm7
+ movdqa %xmm0, %xmm7
+ {load} movdqa %xmm0, %xmm7
+ {store} movdqa %xmm0, %xmm7
+ movdqu %xmm0, %xmm7
+ {load} movdqu %xmm0, %xmm7
+ {store} movdqu %xmm0, %xmm7
+ movq %xmm0, %xmm7
+ {load} movq %xmm0, %xmm7
+ {store} movq %xmm0, %xmm7
+ vmovaps %xmm0, %xmm7
+ {load} vmovaps %xmm0, %xmm7
+ {store} vmovaps %xmm0, %xmm7
+ vmovaps %zmm0, %zmm7
+ {load} vmovaps %zmm0, %zmm7
+ {store} vmovaps %zmm0, %zmm7
+ vmovaps %xmm0, %xmm7{%k7}
+ {load} vmovaps %xmm0, %xmm7{%k7}
+ {store} vmovaps %xmm0, %xmm7{%k7}
+ vmovups %zmm0, %zmm7
+ {load} vmovups %zmm0, %zmm7
+ {store} vmovups %zmm0, %zmm7
+ vmovups %xmm0, %xmm7
+ {load} vmovups %xmm0, %xmm7
+ {store} vmovups %xmm0, %xmm7
+ vmovups %xmm0, %xmm7{%k7}
+ {load} vmovups %xmm0, %xmm7{%k7}
+ {store} vmovups %xmm0, %xmm7{%k7}
+ vmovss %xmm0, %xmm1, %xmm7
+ {load} vmovss %xmm0, %xmm1, %xmm7
+ {store} vmovss %xmm0, %xmm1, %xmm7
+ vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovss %xmm0, %xmm1, %xmm7{%k7}
+ vmovapd %xmm0, %xmm7
+ {load} vmovapd %xmm0, %xmm7
+ {store} vmovapd %xmm0, %xmm7
+ vmovapd %zmm0, %zmm7
+ {load} vmovapd %zmm0, %zmm7
+ {store} vmovapd %zmm0, %zmm7
+ vmovapd %xmm0, %xmm7{%k7}
+ {load} vmovapd %xmm0, %xmm7{%k7}
+ {store} vmovapd %xmm0, %xmm7{%k7}
+ vmovupd %xmm0, %xmm7
+ {load} vmovupd %xmm0, %xmm7
+ {store} vmovupd %xmm0, %xmm7
+ vmovupd %zmm0, %zmm7
+ {load} vmovupd %zmm0, %zmm7
+ {store} vmovupd %zmm0, %zmm7
+ vmovupd %xmm0, %xmm7{%k7}
+ {load} vmovupd %xmm0, %xmm7{%k7}
+ {store} vmovupd %xmm0, %xmm7{%k7}
+ vmovsd %xmm0, %xmm1, %xmm7
+ {load} vmovsd %xmm0, %xmm1, %xmm7
+ {store} vmovsd %xmm0, %xmm1, %xmm7
+ vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {load} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ {store} vmovsd %xmm0, %xmm1, %xmm7{%k7}
+ vmovdqa %xmm0, %xmm7
+ {load} vmovdqa %xmm0, %xmm7
+ {store} vmovdqa %xmm0, %xmm7
+ vmovdqa32 %zmm0, %zmm7
+ {load} vmovdqa32 %zmm0, %zmm7
+ {store} vmovdqa32 %zmm0, %zmm7
+ vmovdqa32 %xmm0, %xmm7
+ {load} vmovdqa32 %xmm0, %xmm7
+ {store} vmovdqa32 %xmm0, %xmm7
+ vmovdqa64 %zmm0, %zmm7
+ {load} vmovdqa64 %zmm0, %zmm7
+ {store} vmovdqa64 %zmm0, %zmm7
+ vmovdqa64 %xmm0, %xmm7
+ {load} vmovdqa64 %xmm0, %xmm7
+ {store} vmovdqa64 %xmm0, %xmm7
+ vmovdqu %xmm0, %xmm7
+ {load} vmovdqu %xmm0, %xmm7
+ {store} vmovdqu %xmm0, %xmm7
+ vmovdqu8 %zmm0, %zmm7
+ {load} vmovdqu8 %zmm0, %zmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu8 %xmm0, %xmm7
+ {load} vmovdqu8 %xmm0, %xmm7
+ {store} vmovdqu8 %zmm0, %zmm7
+ vmovdqu16 %zmm0, %zmm7
+ {load} vmovdqu16 %zmm0, %zmm7
+ {store} vmovdqu16 %zmm0, %zmm7
+ vmovdqu16 %xmm0, %xmm7
+ {load} vmovdqu16 %xmm0, %xmm7
+ {store} vmovdqu16 %xmm0, %xmm7
+ vmovdqu32 %zmm0, %zmm7
+ {load} vmovdqu32 %zmm0, %zmm7
+ {store} vmovdqu32 %zmm0, %zmm7
+ vmovdqu32 %xmm0, %xmm7
+ {load} vmovdqu32 %xmm0, %xmm7
+ {store} vmovdqu32 %xmm0, %xmm7
+ vmovdqu64 %zmm0, %zmm7
+ {load} vmovdqu64 %zmm0, %zmm7
+ {store} vmovdqu64 %zmm0, %zmm7
+ vmovdqu64 %xmm0, %xmm7
+ {load} vmovdqu64 %xmm0, %xmm7
+ {store} vmovdqu64 %xmm0, %xmm7
+ vmovq %xmm0, %xmm7
+ {load} vmovq %xmm0, %xmm7
+ {store} vmovq %xmm0, %xmm7
+ {evex} vmovq %xmm0, %xmm7
+ {load} {evex} vmovq %xmm0, %xmm7
+ {store} {evex} vmovq %xmm0, %xmm7
+
+ bndmov %bnd3, %bnd0
+ {load} bndmov %bnd3, %bnd0
+ {store} bndmov %bnd3, %bnd0
+
movaps (%rax),%xmm2
{load} movaps (%rax),%xmm2
{store} movaps (%rax),%xmm2
Jan Beulich
2018-09-05 13:04:04 UTC
Permalink
The output is identical to that of the LP64 tests. No need to fully
spell this out twice.

gas/
2018-09-05 Jan Beulich <***@suse.com>

testsuite/gas/i386/ilp32/x86-64-opts.d,
testsuite/gas/i386/ilp32/x86-64-opts-intel.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d,
testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Refer to
non-ILP32 output.

--- a/gas/testsuite/gas/i386/ilp32/x86-64-opts-intel.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opts-intel.d
@@ -1,327 +1,4 @@
#source: ../x86-64-opts.s
#objdump: -drwMintel,suffix
#name: x86-64 (ILP32) encoding option (Intel mode)
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd xmm6,xmm4
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss xmm6,xmm4
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-#pass
+#dump: ../x86-64-opts-intel.d
--- a/gas/testsuite/gas/i386/ilp32/x86-64-opts.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opts.d
@@ -1,327 +1,4 @@
#source: ../x86-64-opts.s
#objdump: -drwMsuffix
#name: x86-64 (ILP32) encoding option
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 10 f4 movsd %xmm4,%xmm6
-[ ]*[a-f0-9]+: f2 0f 11 e6 movsd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 10 f4 movss %xmm4,%xmm6
-[ ]*[a-f0-9]+: f3 0f 11 e6 movss.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
-[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-#pass
+#dump: ../x86-64-opts.d
--- a/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts-intel.d
@@ -2,327 +2,4 @@
#as: -msse2avx
#objdump: -drwMintel,suffix
#name: x86-64 (ILP32) encoding option with -msse2avx (Intel mode)
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-[ ]*[a-f0-9]+: 00 d1 add cl,dl
-[ ]*[a-f0-9]+: 02 ca add.s cl,dl
-[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
-[ ]*[a-f0-9]+: 66 03 ca add.s cx,dx
-[ ]*[a-f0-9]+: 01 d1 add ecx,edx
-[ ]*[a-f0-9]+: 03 ca add.s ecx,edx
-[ ]*[a-f0-9]+: 48 01 d1 add rcx,rdx
-[ ]*[a-f0-9]+: 48 03 ca add.s rcx,rdx
-[ ]*[a-f0-9]+: 10 d1 adc cl,dl
-[ ]*[a-f0-9]+: 12 ca adc.s cl,dl
-[ ]*[a-f0-9]+: 66 11 d1 adc cx,dx
-[ ]*[a-f0-9]+: 66 13 ca adc.s cx,dx
-[ ]*[a-f0-9]+: 11 d1 adc ecx,edx
-[ ]*[a-f0-9]+: 13 ca adc.s ecx,edx
-[ ]*[a-f0-9]+: 48 11 d1 adc rcx,rdx
-[ ]*[a-f0-9]+: 48 13 ca adc.s rcx,rdx
-[ ]*[a-f0-9]+: 20 d1 and cl,dl
-[ ]*[a-f0-9]+: 22 ca and.s cl,dl
-[ ]*[a-f0-9]+: 66 21 d1 and cx,dx
-[ ]*[a-f0-9]+: 66 23 ca and.s cx,dx
-[ ]*[a-f0-9]+: 21 d1 and ecx,edx
-[ ]*[a-f0-9]+: 23 ca and.s ecx,edx
-[ ]*[a-f0-9]+: 48 21 d1 and rcx,rdx
-[ ]*[a-f0-9]+: 48 23 ca and.s rcx,rdx
-[ ]*[a-f0-9]+: 38 d1 cmp cl,dl
-[ ]*[a-f0-9]+: 3a ca cmp.s cl,dl
-[ ]*[a-f0-9]+: 66 39 d1 cmp cx,dx
-[ ]*[a-f0-9]+: 66 3b ca cmp.s cx,dx
-[ ]*[a-f0-9]+: 39 d1 cmp ecx,edx
-[ ]*[a-f0-9]+: 3b ca cmp.s ecx,edx
-[ ]*[a-f0-9]+: 48 39 d1 cmp rcx,rdx
-[ ]*[a-f0-9]+: 48 3b ca cmp.s rcx,rdx
-[ ]*[a-f0-9]+: 88 d1 mov cl,dl
-[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
-[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
-[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
-[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
-[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
-[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
-[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
-[ ]*[a-f0-9]+: 08 d1 or cl,dl
-[ ]*[a-f0-9]+: 0a ca or.s cl,dl
-[ ]*[a-f0-9]+: 66 09 d1 or cx,dx
-[ ]*[a-f0-9]+: 66 0b ca or.s cx,dx
-[ ]*[a-f0-9]+: 09 d1 or ecx,edx
-[ ]*[a-f0-9]+: 0b ca or.s ecx,edx
-[ ]*[a-f0-9]+: 48 09 d1 or rcx,rdx
-[ ]*[a-f0-9]+: 48 0b ca or.s rcx,rdx
-[ ]*[a-f0-9]+: 18 d1 sbb cl,dl
-[ ]*[a-f0-9]+: 1a ca sbb.s cl,dl
-[ ]*[a-f0-9]+: 66 19 d1 sbb cx,dx
-[ ]*[a-f0-9]+: 66 1b ca sbb.s cx,dx
-[ ]*[a-f0-9]+: 19 d1 sbb ecx,edx
-[ ]*[a-f0-9]+: 1b ca sbb.s ecx,edx
-[ ]*[a-f0-9]+: 48 19 d1 sbb rcx,rdx
-[ ]*[a-f0-9]+: 48 1b ca sbb.s rcx,rdx
-[ ]*[a-f0-9]+: 28 d1 sub cl,dl
-[ ]*[a-f0-9]+: 2a ca sub.s cl,dl
-[ ]*[a-f0-9]+: 66 29 d1 sub cx,dx
-[ ]*[a-f0-9]+: 66 2b ca sub.s cx,dx
-[ ]*[a-f0-9]+: 29 d1 sub ecx,edx
-[ ]*[a-f0-9]+: 2b ca sub.s ecx,edx
-[ ]*[a-f0-9]+: 48 29 d1 sub rcx,rdx
-[ ]*[a-f0-9]+: 48 2b ca sub.s rcx,rdx
-[ ]*[a-f0-9]+: 30 d1 xor cl,dl
-[ ]*[a-f0-9]+: 32 ca xor.s cl,dl
-[ ]*[a-f0-9]+: 66 31 d1 xor cx,dx
-[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
-[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
-[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
-[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
-[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s xmm6,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
-#pass
+#dump: ../x86-64-sse2avx-opts-intel.d
--- a/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-sse2avx-opts.d
@@ -2,327 +2,4 @@
#as: -msse2avx
#objdump: -drwMsuffix
#name: x86-64 (ILP32) encoding option with -msse2avx
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
-[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
-[ ]*[a-f0-9]+: 66 03 ca addw.s %dx,%cx
-[ ]*[a-f0-9]+: 01 d1 addl %edx,%ecx
-[ ]*[a-f0-9]+: 03 ca addl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 01 d1 addq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 03 ca addq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 10 d1 adcb %dl,%cl
-[ ]*[a-f0-9]+: 12 ca adcb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 11 d1 adcw %dx,%cx
-[ ]*[a-f0-9]+: 66 13 ca adcw.s %dx,%cx
-[ ]*[a-f0-9]+: 11 d1 adcl %edx,%ecx
-[ ]*[a-f0-9]+: 13 ca adcl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 11 d1 adcq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 13 ca adcq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 20 d1 andb %dl,%cl
-[ ]*[a-f0-9]+: 22 ca andb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 21 d1 andw %dx,%cx
-[ ]*[a-f0-9]+: 66 23 ca andw.s %dx,%cx
-[ ]*[a-f0-9]+: 21 d1 andl %edx,%ecx
-[ ]*[a-f0-9]+: 23 ca andl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 21 d1 andq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 23 ca andq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 38 d1 cmpb %dl,%cl
-[ ]*[a-f0-9]+: 3a ca cmpb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 39 d1 cmpw %dx,%cx
-[ ]*[a-f0-9]+: 66 3b ca cmpw.s %dx,%cx
-[ ]*[a-f0-9]+: 39 d1 cmpl %edx,%ecx
-[ ]*[a-f0-9]+: 3b ca cmpl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 39 d1 cmpq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 3b ca cmpq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
-[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
-[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
-[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
-[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 08 d1 orb %dl,%cl
-[ ]*[a-f0-9]+: 0a ca orb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 09 d1 orw %dx,%cx
-[ ]*[a-f0-9]+: 66 0b ca orw.s %dx,%cx
-[ ]*[a-f0-9]+: 09 d1 orl %edx,%ecx
-[ ]*[a-f0-9]+: 0b ca orl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 09 d1 orq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 0b ca orq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 18 d1 sbbb %dl,%cl
-[ ]*[a-f0-9]+: 1a ca sbbb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 19 d1 sbbw %dx,%cx
-[ ]*[a-f0-9]+: 66 1b ca sbbw.s %dx,%cx
-[ ]*[a-f0-9]+: 19 d1 sbbl %edx,%ecx
-[ ]*[a-f0-9]+: 1b ca sbbl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 19 d1 sbbq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 1b ca sbbq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 28 d1 subb %dl,%cl
-[ ]*[a-f0-9]+: 2a ca subb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 29 d1 subw %dx,%cx
-[ ]*[a-f0-9]+: 66 2b ca subw.s %dx,%cx
-[ ]*[a-f0-9]+: 29 d1 subl %edx,%ecx
-[ ]*[a-f0-9]+: 2b ca subl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 29 d1 subq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 2b ca subq.s %rdx,%rcx
-[ ]*[a-f0-9]+: 30 d1 xorb %dl,%cl
-[ ]*[a-f0-9]+: 32 ca xorb.s %dl,%cl
-[ ]*[a-f0-9]+: 66 31 d1 xorw %dx,%cx
-[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
-[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
-[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
-[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
-[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
-[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 cb 11 e6 vmovsd.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 ca 11 e6 vmovss.s %xmm4,%xmm6,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
-[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
-#pass
+#dump: ../x86-64-sse2avx-opts.d
Jan Beulich
2018-09-05 13:04:30 UTC
Permalink
"x86: improve operand reversal" has fixed a number of issues with the .s
pseudo-suffix too. As an optional change, test cases get added here to
cover this.

gas/
2018-09-05 Jan Beulich <***@suse.com>

* testsuite/gas/i386/opts.s: Add mov, FPU, and vmov* tests.
* testsuite/gas/i386/x86-64-opts.s: Likewise, plus bndmov.
* testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d,
testsuite/gas/i386/sse2avx-opts.d,
testsuite/gas/i386/sse2avx-opts-intel.d,
testsuite/gas/i386/x86-64-opts.d,
testsuite/gas/i386/x86-64-opts-intel.d,
testsuite/gas/i386/x86-64-sse2avx-opts.d,
testsuite/gas/i386/x86-64-sse2avx-opts-intel.d: Adjust
expectations.

--- a/gas/testsuite/gas/i386/opts-intel.d
+++ b/gas/testsuite/gas/i386/opts-intel.d
@@ -116,6 +116,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -166,6 +194,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1
[ ]*[a-f0-9]+: 00 d1 add cl,dl
--- a/gas/testsuite/gas/i386/opts.d
+++ b/gas/testsuite/gas/i386/opts.d
@@ -115,6 +115,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -165,6 +193,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
--- a/gas/testsuite/gas/i386/opts.s
+++ b/gas/testsuite/gas/i386/opts.s
@@ -114,6 +114,38 @@ _start:
xorl %edx,%ecx
xorl.s %edx,%ecx

+# Tests for moves which cannot be changed
+ mov 0x12345678, %eax
+ mov.s 0x12345678, %eax
+ mov %eax, 0x12345678
+ mov.s %eax, 0x12345678
+ mov %eax, (%edi)
+ mov.s %eax, (%edi)
+ mov (%edi), %eax
+ mov.s (%edi), %eax
+ mov %cr0, %eax
+ mov.s %cr0, %eax
+ mov %eax, %cr7
+ mov.s %eax, %cr7
+ mov %dr0, %eax
+ mov.s %dr0, %eax
+ mov %eax, %dr7
+ mov.s %eax, %dr7
+
+# Tests for op st, st
+ fadd %st, %st
+ fadd.s %st, %st
+ fdiv %st, %st
+ fdiv.s %st, %st
+ fdivr %st, %st
+ fdivr.s %st, %st
+ fmul %st, %st
+ fmul.s %st, %st
+ fsub %st, %st
+ fsub.s %st, %st
+ fsubr %st, %st
+ fsubr.s %st, %st
+
# Tests for op ymm, ymm
vmovapd %ymm4,%ymm6
vmovapd.s %ymm4,%ymm6
@@ -172,6 +204,80 @@ _start:
movq %mm0,%mm4
movq.s %mm0,%mm4

+# Tests for op zmm, zmm
+ vmovapd %zmm4,%zmm6
+ vmovapd.s %zmm4,%zmm6
+ vmovaps %zmm4,%zmm6
+ vmovaps.s %zmm4,%zmm6
+ vmovdqa32 %zmm4,%zmm6
+ vmovdqa32.s %zmm4,%zmm6
+ vmovdqa64 %zmm4,%zmm6
+ vmovdqa64.s %zmm4,%zmm6
+ vmovdqu8 %zmm4,%zmm6
+ vmovdqu8.s %zmm4,%zmm6
+ vmovdqu16 %zmm4,%zmm6
+ vmovdqu16.s %zmm4,%zmm6
+ vmovdqu32 %zmm4,%zmm6
+ vmovdqu32.s %zmm4,%zmm6
+ vmovdqu64 %zmm4,%zmm6
+ vmovdqu64.s %zmm4,%zmm6
+ vmovupd %zmm4,%zmm6
+ vmovupd.s %zmm4,%zmm6
+ vmovups %zmm4,%zmm6
+ vmovups.s %zmm4,%zmm6
+
+# Tests for EVEX forms of op ymm, ymm
+ vmovapd %ymm4,%ymm6{%k7}
+ vmovapd.s %ymm4,%ymm6{%k7}
+ vmovaps %ymm4,%ymm6{%k7}
+ vmovaps.s %ymm4,%ymm6{%k7}
+ vmovdqa32 %ymm4,%ymm6
+ vmovdqa32.s %ymm4,%ymm6
+ vmovdqa64 %ymm4,%ymm6
+ vmovdqa64.s %ymm4,%ymm6
+ vmovdqu8 %ymm4,%ymm6
+ vmovdqu8.s %ymm4,%ymm6
+ vmovdqu16 %ymm4,%ymm6
+ vmovdqu16.s %ymm4,%ymm6
+ vmovdqu32 %ymm4,%ymm6
+ vmovdqu32.s %ymm4,%ymm6
+ vmovdqu64 %ymm4,%ymm6
+ vmovdqu64.s %ymm4,%ymm6
+ vmovupd %ymm4,%ymm6{%k7}
+ vmovupd.s %ymm4,%ymm6{%k7}
+ vmovups %ymm4,%ymm6{%k7}
+ vmovups.s %ymm4,%ymm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm
+ vmovapd %xmm4,%xmm6{%k7}
+ vmovapd.s %xmm4,%xmm6{%k7}
+ vmovaps %xmm4,%xmm6{%k7}
+ vmovaps.s %xmm4,%xmm6{%k7}
+ vmovdqa32 %xmm4,%xmm6
+ vmovdqa32.s %xmm4,%xmm6
+ vmovdqa64 %xmm4,%xmm6
+ vmovdqa64.s %xmm4,%xmm6
+ vmovdqu8 %xmm4,%xmm6
+ vmovdqu8.s %xmm4,%xmm6
+ vmovdqu16 %xmm4,%xmm6
+ vmovdqu16.s %xmm4,%xmm6
+ vmovdqu32 %xmm4,%xmm6
+ vmovdqu32.s %xmm4,%xmm6
+ vmovdqu64 %xmm4,%xmm6
+ vmovdqu64.s %xmm4,%xmm6
+ {evex} vmovq %xmm4,%xmm6
+ {evex} vmovq.s %xmm4,%xmm6
+ vmovupd %xmm4,%xmm6{%k7}
+ vmovupd.s %xmm4,%xmm6{%k7}
+ vmovups %xmm4,%xmm6{%k7}
+ vmovups.s %xmm4,%xmm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm, xmm
+ vmovsd %xmm4,%xmm6,%xmm2{%k7}
+ vmovsd.s %xmm4,%xmm6,%xmm2{%k7}
+ vmovss %xmm4,%xmm6,%xmm2{%k7}
+ vmovss.s %xmm4,%xmm6,%xmm2{%k7}
+
# Tests for op bnd, bnd
bndmov %bnd1,%bnd2
bndmov.s %bnd1,%bnd2
--- a/gas/testsuite/gas/i386/sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/sse2avx-opts-intel.d
@@ -117,6 +117,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xor.s cx,dx
[ ]*[a-f0-9]+: 31 d1 xor ecx,edx
[ ]*[a-f0-9]+: 33 ca xor.s ecx,edx
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a1 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[edi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[edi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov eax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,eax
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov eax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,eax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -167,6 +195,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1
[ ]*[a-f0-9]+: 00 d1 add cl,dl
--- a/gas/testsuite/gas/i386/sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/sse2avx-opts.d
@@ -117,6 +117,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 33 ca xorw.s %dx,%cx
[ ]*[a-f0-9]+: 31 d1 xorl %edx,%ecx
[ ]*[a-f0-9]+: 33 ca xorl.s %edx,%ecx
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a1 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a3 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%edi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%edi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movl %cr0,%eax
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movl %eax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 21 c0 movl %db0,%eax
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movl %eax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -167,6 +195,72 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2
[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
--- a/gas/testsuite/gas/i386/x86-64-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-opts-intel.d
@@ -152,6 +152,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -202,6 +238,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov bnd3,bnd0
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s bnd3,bnd0
[ ]*[a-f0-9]+: 00 d1 add cl,dl
[ ]*[a-f0-9]+: 02 ca add.s cl,dl
[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
--- a/gas/testsuite/gas/i386/x86-64-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-opts.d
@@ -151,6 +151,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -201,6 +237,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov %bnd0,%bnd3
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s %bnd0,%bnd3
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
--- a/gas/testsuite/gas/i386/x86-64-opts.s
+++ b/gas/testsuite/gas/i386/x86-64-opts.s
@@ -150,6 +150,46 @@ _start:
xorq %rdx,%rcx
xorq.s %rdx,%rcx

+# Tests for moves which cannot be changed
+ mov 0x12345678, %eax
+ mov.s 0x12345678, %eax
+ mov %eax, 0x12345678
+ mov.s %eax, 0x12345678
+ mov 0x123456789abcdef0, %eax
+ mov.s 0x123456789abcdef0, %eax
+ mov %eax, 0x123456789abcdef0
+ mov.s %eax, 0x123456789abcdef0
+ movabs 0x123456789abcdef0, %eax
+ movabs.s 0x123456789abcdef0, %eax
+ movabs %eax, 0x123456789abcdef0
+ movabs.s %eax, 0x123456789abcdef0
+ mov %eax, (%rdi)
+ mov.s %eax, (%rdi)
+ mov (%rdi), %eax
+ mov.s (%rdi), %eax
+ mov %cr0, %rax
+ mov.s %cr0, %rax
+ mov %rax, %cr7
+ mov.s %rax, %cr7
+ mov %dr0, %rax
+ mov.s %dr0, %rax
+ mov %rax, %dr7
+ mov.s %rax, %dr7
+
+# Tests for op st, st
+ fadd %st, %st
+ fadd.s %st, %st
+ fdiv %st, %st
+ fdiv.s %st, %st
+ fdivr %st, %st
+ fdivr.s %st, %st
+ fmul %st, %st
+ fmul.s %st, %st
+ fsub %st, %st
+ fsub.s %st, %st
+ fsubr %st, %st
+ fsubr.s %st, %st
+
# Tests for op ymm, ymm
vmovapd %ymm4,%ymm6
vmovapd.s %ymm4,%ymm6
@@ -208,6 +248,84 @@ _start:
movq %mm0,%mm4
movq.s %mm0,%mm4

+# Tests for op zmm, zmm
+ vmovapd %zmm4,%zmm6
+ vmovapd.s %zmm4,%zmm6
+ vmovaps %zmm4,%zmm6
+ vmovaps.s %zmm4,%zmm6
+ vmovdqa32 %zmm4,%zmm6
+ vmovdqa32.s %zmm4,%zmm6
+ vmovdqa64 %zmm4,%zmm6
+ vmovdqa64.s %zmm4,%zmm6
+ vmovdqu8 %zmm4,%zmm6
+ vmovdqu8.s %zmm4,%zmm6
+ vmovdqu16 %zmm4,%zmm6
+ vmovdqu16.s %zmm4,%zmm6
+ vmovdqu32 %zmm4,%zmm6
+ vmovdqu32.s %zmm4,%zmm6
+ vmovdqu64 %zmm4,%zmm6
+ vmovdqu64.s %zmm4,%zmm6
+ vmovupd %zmm4,%zmm6
+ vmovupd.s %zmm4,%zmm6
+ vmovups %zmm4,%zmm6
+ vmovups.s %zmm4,%zmm6
+
+# Tests for EVEX forms of op ymm, ymm
+ vmovapd %ymm4,%ymm6{%k7}
+ vmovapd.s %ymm4,%ymm6{%k7}
+ vmovaps %ymm4,%ymm6{%k7}
+ vmovaps.s %ymm4,%ymm6{%k7}
+ vmovdqa32 %ymm4,%ymm6
+ vmovdqa32.s %ymm4,%ymm6
+ vmovdqa64 %ymm4,%ymm6
+ vmovdqa64.s %ymm4,%ymm6
+ vmovdqu8 %ymm4,%ymm6
+ vmovdqu8.s %ymm4,%ymm6
+ vmovdqu16 %ymm4,%ymm6
+ vmovdqu16.s %ymm4,%ymm6
+ vmovdqu32 %ymm4,%ymm6
+ vmovdqu32.s %ymm4,%ymm6
+ vmovdqu64 %ymm4,%ymm6
+ vmovdqu64.s %ymm4,%ymm6
+ vmovupd %ymm4,%ymm6{%k7}
+ vmovupd.s %ymm4,%ymm6{%k7}
+ vmovups %ymm4,%ymm6{%k7}
+ vmovups.s %ymm4,%ymm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm
+ vmovapd %xmm4,%xmm6{%k7}
+ vmovapd.s %xmm4,%xmm6{%k7}
+ vmovaps %xmm4,%xmm6{%k7}
+ vmovaps.s %xmm4,%xmm6{%k7}
+ vmovdqa32 %xmm4,%xmm6
+ vmovdqa32.s %xmm4,%xmm6
+ vmovdqa64 %xmm4,%xmm6
+ vmovdqa64.s %xmm4,%xmm6
+ vmovdqu8 %xmm4,%xmm6
+ vmovdqu8.s %xmm4,%xmm6
+ vmovdqu16 %xmm4,%xmm6
+ vmovdqu16.s %xmm4,%xmm6
+ vmovdqu32 %xmm4,%xmm6
+ vmovdqu32.s %xmm4,%xmm6
+ vmovdqu64 %xmm4,%xmm6
+ vmovdqu64.s %xmm4,%xmm6
+ {evex} vmovq %xmm4,%xmm6
+ {evex} vmovq.s %xmm4,%xmm6
+ vmovupd %xmm4,%xmm6{%k7}
+ vmovupd.s %xmm4,%xmm6{%k7}
+ vmovups %xmm4,%xmm6{%k7}
+ vmovups.s %xmm4,%xmm6{%k7}
+
+# Tests for EVEX forms op xmm, xmm, xmm
+ vmovsd %xmm4,%xmm6,%xmm2{%k7}
+ vmovsd.s %xmm4,%xmm6,%xmm2{%k7}
+ vmovss %xmm4,%xmm6,%xmm2{%k7}
+ vmovss.s %xmm4,%xmm6,%xmm2{%k7}
+
+# Tests for op bnd, bnd
+ bndmov %bnd0, %bnd3
+ bndmov.s %bnd0, %bnd3
+
.intel_syntax noprefix

# Tests for op reg, reg
--- a/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
@@ -153,6 +153,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
[ ]*[a-f0-9]+: 48 31 d1 xor rcx,rdx
[ ]*[a-f0-9]+: 48 33 ca xor.s rcx,rdx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 mov eax,DWORD PTR ds:0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 mov DWORD PTR ds:0x12345678,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabs eax,DWORD PTR ds:0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabs DWORD PTR ds:0x123456789abcdef0,eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 89 07 mov DWORD PTR \[rdi\],eax
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 8b 07 mov eax,DWORD PTR \[rdi\]
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 20 c0 mov rax,cr0
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 22 f8 mov cr7,rax
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 21 c0 mov rax,db0
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: 0f 23 f8 mov db7,rax
+[ ]*[a-f0-9]+: d8 c0 fadd st,st\(0\)
+[ ]*[a-f0-9]+: dc c0 fadd st\(0\),st
+[ ]*[a-f0-9]+: d8 f0 fdiv st,st\(0\)
+[ ]*[a-f0-9]+: dc f0 fdivr st\(0\),st
+[ ]*[a-f0-9]+: d8 f8 fdivr st,st\(0\)
+[ ]*[a-f0-9]+: dc f8 fdiv st\(0\),st
+[ ]*[a-f0-9]+: d8 c8 fmul st,st\(0\)
+[ ]*[a-f0-9]+: dc c8 fmul st\(0\),st
+[ ]*[a-f0-9]+: d8 e0 fsub st,st\(0\)
+[ ]*[a-f0-9]+: dc e0 fsubr st\(0\),st
+[ ]*[a-f0-9]+: d8 e8 fsubr st,st\(0\)
+[ ]*[a-f0-9]+: dc e8 fsub st\(0\),st
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
@@ -203,6 +239,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s zmm6,zmm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s ymm6,ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s ymm6\{k7\},ymm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s xmm6\{k7\},xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s xmm2\{k7\},xmm6,xmm4
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov bnd3,bnd0
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s bnd3,bnd0
[ ]*[a-f0-9]+: 00 d1 add cl,dl
[ ]*[a-f0-9]+: 02 ca add.s cl,dl
[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
--- a/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
@@ -153,6 +153,42 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
[ ]*[a-f0-9]+: 48 31 d1 xorq %rdx,%rcx
[ ]*[a-f0-9]+: 48 33 ca xorq.s %rdx,%rcx
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 8b 04 25 78 56 34 12 movl 0x12345678,%eax
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: 89 04 25 78 56 34 12 movl %eax,0x12345678
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a1 f0 de bc 9a 78 56 34 12 movabsl 0x123456789abcdef0,%eax
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: a3 f0 de bc 9a 78 56 34 12 movabsl %eax,0x123456789abcdef0
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 89 07 movl %eax,\(%rdi\)
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 8b 07 movl \(%rdi\),%eax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 20 c0 movq %cr0,%rax
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 22 f8 movq %rax,%cr7
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 21 c0 movq %db0,%rax
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: 0f 23 f8 movq %rax,%db7
+[ ]*[a-f0-9]+: d8 c0 fadd %st\(0\),%st
+[ ]*[a-f0-9]+: dc c0 fadd %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
+[ ]*[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
+[ ]*[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 c8 fmul %st\(0\),%st
+[ ]*[a-f0-9]+: dc c8 fmul %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e0 fsub %st\(0\),%st
+[ ]*[a-f0-9]+: dc e0 fsub %st,%st\(0\)
+[ ]*[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
+[ ]*[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
@@ -203,6 +239,74 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
+[ ]*[a-f0-9]+: 62 f1 fd 48 28 f4 vmovapd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 29 e6 vmovapd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 28 f4 vmovaps %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 29 e6 vmovaps.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 6f f4 vmovdqa32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7d 48 7f e6 vmovdqa32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 6f f4 vmovdqa64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 7f e6 vmovdqa64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 6f f4 vmovdqu8 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7f 48 7f e6 vmovdqu8.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 6f f4 vmovdqu16 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 ff 48 7f e6 vmovdqu16.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 6f f4 vmovdqu32 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7e 48 7f e6 vmovdqu32.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 6f f4 vmovdqu64 %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fe 48 7f e6 vmovdqu64.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 10 f4 vmovupd %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 48 11 e6 vmovupd.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 10 f4 vmovups %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 7c 48 11 e6 vmovups.s %zmm4,%zmm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 28 f4 vmovapd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 29 e6 vmovapd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 28 f4 vmovaps %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 29 e6 vmovaps.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 28 6f f4 vmovdqa32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7d 28 7f e6 vmovdqa32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 6f f4 vmovdqa64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 28 7f e6 vmovdqa64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 6f f4 vmovdqu8 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7f 28 7f e6 vmovdqu8.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 6f f4 vmovdqu16 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 ff 28 7f e6 vmovdqu16.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 6f f4 vmovdqu32 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 7e 28 7f e6 vmovdqu32.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 6f f4 vmovdqu64 %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fe 28 7f e6 vmovdqu64.s %ymm4,%ymm6
+[ ]*[a-f0-9]+: 62 f1 fd 2f 10 f4 vmovupd %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 2f 11 e6 vmovupd.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 10 f4 vmovups %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 2f 11 e6 vmovups.s %ymm4,%ymm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 28 f4 vmovapd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 29 e6 vmovapd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 28 f4 vmovaps %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 29 e6 vmovaps.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7d 08 7f e6 vmovdqa32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 6f f4 vmovdqa64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 7f e6 vmovdqa64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 6f f4 vmovdqu8 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7f 08 7f e6 vmovdqu8.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 6f f4 vmovdqu16 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 ff 08 7f e6 vmovdqu16.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 7e 08 7f e6 vmovdqu32.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 6f f4 vmovdqu64 %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7f e6 vmovdqu64.s %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 e6 vmovq %xmm4,%xmm6
+[ ]*[a-f0-9]+: 62 f1 fd 0f 10 f4 vmovupd %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 fd 0f 11 e6 vmovupd.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 10 f4 vmovups %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7c 0f 11 e6 vmovups.s %xmm4,%xmm6\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 10 d4 vmovsd %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 cf 0f 11 e2 vmovsd.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 10 d4 vmovss %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 4e 0f 11 e2 vmovss.s %xmm4,%xmm6,%xmm2\{%k7\}
+[ ]*[a-f0-9]+: 66 0f 1a d8 bndmov %bnd0,%bnd3
+[ ]*[a-f0-9]+: 66 0f 1b c3 bndmov.s %bnd0,%bnd3
[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
Jan Beulich
2018-09-05 13:05:07 UTC
Permalink
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.

Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.

gas/
2018-09-05 Jan Beulich <***@suse.com>

* config/tc-i386.c (operand_size_match): Mirror
.reg/.regsimd/.acc handling from forward to reverse case.
(build_vex_prefix): Check first and last operand types are equal
and also consider .d for swapping operands for VEX2 encoding.
(match_template): Clear found_reverse_match on every iteration.
Use Opcode_SIMD_FloatD and Opcode_SIMD_IntD.
* testsuite/gas/i386/pseudos.s,
testsuite/gas/i386/x86-64-pseudos.s: Add kmov* tests.
* testsuite/gas/i386/pseudos.d,
testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations.

opcodes/
2018-09-05 Jan Beulich <***@suse.com>

* i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
Fold load and store templates where possible, adding D. Drop
IgnoreSize where it was pointlessly present. Drop redundant
*word.
* i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2057,11 +2057,18 @@ mismatch:

for (j = 0; j < 2; j++)
{
- if ((t->operand_types[j].bitfield.reg
- || t->operand_types[j].bitfield.acc)
+ if (t->operand_types[j].bitfield.reg
&& !match_operand_size (t, j, !j))
goto mismatch;

+ if (t->operand_types[j].bitfield.regsimd
+ && !match_simd_size (t, j, !j))
+ goto mismatch;
+
+ if (t->operand_types[j].bitfield.acc
+ && (!match_operand_size (t, j, !j) || !match_simd_size (t, j, !j)))
+ goto mismatch;
+
if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
goto mismatch;
}
@@ -3359,8 +3366,9 @@ build_vex_prefix (const insn_template *t
if (i.vec_encoding != vex_encoding_vex3
&& i.dir_encoding == dir_encoding_default
&& i.operands == i.reg_operands
+ && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
&& i.tm.opcode_modifier.vexopcode == VEX0F
- && i.tm.opcode_modifier.load
+ && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
&& i.rex == REX_B)
{
unsigned int xchg = i.operands - 1;
@@ -3381,8 +3389,11 @@ build_vex_prefix (const insn_template *t
i.rm.regmem = i.rm.reg;
i.rm.reg = xchg;

- /* Use the next insn. */
- i.tm = t[1];
+ if (i.tm.opcode_modifier.d)
+ i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
+ ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
+ else /* Use the next insn. */
+ i.tm = t[1];
}

if (i.tm.opcode_modifier.vex == VEXScalar)
@@ -5527,6 +5538,7 @@ match_template (char mnem_suffix)
for (t = current_templates->start; t < current_templates->end; t++)
{
addr_prefix_disp = -1;
+ found_reverse_match = 0;

if (i.operands != t->operands)
continue;
@@ -5777,6 +5789,13 @@ check_reverse:
found_reverse_match = 0;
else if (operand_types[0].bitfield.tbyte)
found_reverse_match = Opcode_FloatD;
+ else if (operand_types[0].bitfield.xmmword
+ || operand_types[1].bitfield.xmmword
+ || operand_types[0].bitfield.regmmx
+ || operand_types[1].bitfield.regmmx
+ || is_any_vex_encoding(t))
+ found_reverse_match = (t->base_opcode & 0xee) != 0x6e
+ ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
else
found_reverse_match = Opcode_D;
if (t->opcode_modifier.floatr)
@@ -5847,10 +5866,7 @@ check_reverse:
slip through to break. */
}
if (!found_cpu_match)
- {
- found_reverse_match = 0;
- continue;
- }
+ continue;

/* Check if vector and VEX operands are valid. */
if (check_VecOperands (t) || VEX_check_operands (t))
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -68,6 +68,26 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+[a-f0-9]+: 0f 21 c7 mov %db0,%edi
+[a-f0-9]+: 0f 23 f8 mov %eax,%db7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+[a-f0-9]+: 11 07 adc %eax,\(%edi\)
+[a-f0-9]+: 13 07 adc \(%edi\),%eax
+[a-f0-9]+: 11 07 adc %eax,\(%edi\)
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -65,6 +65,26 @@ _start:
{load} mov %eax, %dr7
{store} mov %dr0, %edi
{store} mov %eax, %dr7
+ {load} kmovb %k0, %edi
+ {load} kmovb %eax, %k7
+ {store} kmovb %k0, %edi
+ {store} kmovb %eax, %k7
+ {load} kmovd %k0, %edi
+ {load} kmovd %eax, %k7
+ {store} kmovd %k0, %edi
+ {store} kmovd %eax, %k7
+ {load} kmovw %k0, %edi
+ {load} kmovw %eax, %k7
+ {store} kmovw %k0, %edi
+ {store} kmovw %eax, %k7
+ {load} kmovb %k0, %k7
+ {store} kmovb %k0, %k7
+ {load} kmovd %k0, %k7
+ {store} kmovd %k0, %k7
+ {load} kmovq %k0, %k7
+ {store} kmovq %k0, %k7
+ {load} kmovw %k0, %k7
+ {store} kmovw %k0, %k7
{load} adc %eax, (%edi)
{load} adc (%edi), %eax
{store} adc %eax, (%edi)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -76,6 +76,30 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+[a-f0-9]+: 0f 21 c7 mov %db0,%rdi
+[a-f0-9]+: 0f 23 f8 mov %rax,%db7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
+ +[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
+ +[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
+ +[a-f0-9]+: c4 e1 fb 93 f8 kmovq %k0,%rdi
+ +[a-f0-9]+: c4 e1 fb 92 f8 kmovq %rax,%k7
+ +[a-f0-9]+: c4 e1 fb 93 f8 kmovq %k0,%rdi
+ +[a-f0-9]+: c4 e1 fb 92 f8 kmovq %rax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
+ +[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+ +[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
+[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
+[a-f0-9]+: 13 07 adc \(%rdi\),%eax
+[a-f0-9]+: 11 07 adc %eax,\(%rdi\)
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -73,6 +73,30 @@ _start:
{load} mov %rax, %dr7
{store} mov %dr0, %rdi
{store} mov %rax, %dr7
+ {load} kmovb %k0, %edi
+ {load} kmovb %eax, %k7
+ {store} kmovb %k0, %edi
+ {store} kmovb %eax, %k7
+ {load} kmovd %k0, %edi
+ {load} kmovd %eax, %k7
+ {store} kmovd %k0, %edi
+ {store} kmovd %eax, %k7
+ {load} kmovq %k0, %rdi
+ {load} kmovq %rax, %k7
+ {store} kmovq %k0, %rdi
+ {store} kmovq %rax, %k7
+ {load} kmovw %k0, %edi
+ {load} kmovw %eax, %k7
+ {store} kmovw %k0, %edi
+ {store} kmovw %eax, %k7
+ {load} kmovb %k0, %k7
+ {store} kmovb %k0, %k7
+ {load} kmovd %k0, %k7
+ {store} kmovd %k0, %k7
+ {load} kmovq %k0, %k7
+ {store} kmovq %k0, %k7
+ {load} kmovw %k0, %k7
+ {store} kmovw %k0, %k7
{load} adc %eax, (%rdi)
{load} adc (%rdi), %eax
{store} adc %eax, (%rdi)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -861,6 +861,8 @@ typedef struct insn_template
unset if Regmem --> Reg. */
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */

/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -941,18 +941,12 @@ emms, 0, 0xf77, None, 2, CpuMMX, No_bSuf
// copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's
// spec). AMD's spec, having been in existence for much longer, failed to
// recognize that and specified movd for 32- and 64-bit operations.
-movd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|Qword|BaseIndex, RegXMM }
-movd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
-movd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { RegXMM, Qword|Reg64|BaseIndex }
-movd, 2, 0x660f6e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex, RegXMM }
-movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-movd, 2, 0x660f7e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Reg64|Qword|BaseIndex }
-movd, 2, 0xf6e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegMMX }
-movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex, RegMMX }
-movd, 2, 0xf7e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg32|Dword|Unspecified|BaseIndex }
-movd, 2, 0xf7e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegMMX, Reg64|Qword|BaseIndex }
+movd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM }
+movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|BaseIndex, RegXMM }
+movd, 2, 0x660f6e, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
+movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|BaseIndex, RegXMM }
+movd, 2, 0xf6e, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegMMX }
+movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|BaseIndex, RegMMX }
// In the 64bit mode the short form mov immediate is redefined to have
// 64bit displacement value. We put the 64bit displacement first and
// we only mark constants larger than 32bit as Disp64.
@@ -962,16 +956,12 @@ movq, 2, 0xc6, 0x0, 1, Cpu64, W|Modrm|Si
movq, 2, 0xb0, None, 1, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
movq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Qword|Unspecified|BaseIndex, RegXMM }
-movq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { RegXMM, Reg64|Qword|Unspecified|BaseIndex }
+movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM }
movq, 2, 0xf30f7e, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM }
movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM }
-movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|Qword|BaseIndex, RegXMM }
-movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Unspecified|Qword|BaseIndex }
-movq, 2, 0xf6f, None, 2, CpuMMX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX }
-movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|RegMMX }
-movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|Qword|BaseIndex, RegMMX }
-movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegMMX, Reg64|Unspecified|Qword|BaseIndex }
+movq, 2, 0x660f6e, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
+movq, 2, 0xf6f, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX }
+movq, 2, 0xf6e, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX }
// The segment register moves accept Reg64 so that a segment register
// can be copied to a 64 bit register, and vice versa.
movq, 2, 0x8c, None, 1, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2|SReg3, Reg64|RegMem }
@@ -1217,22 +1207,18 @@ minps, 2, 0x5d, None, 1, CpuAVX, Modrm|V
minps, 2, 0xf5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
minss, 2, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movaps, 2, 0x28, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movaps, 2, 0xf28, None, 2, CpuSSE, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movaps, 2, 0xf29, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movaps, 2, 0x28, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movaps, 2, 0xf28, None, 2, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movhlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
movhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movhps, 2, 0x17, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movhps, 2, 0xf17, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movhps, 2, 0xf16, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movlhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movlps, 2, 0xf13, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movlps, 2, 0xf12, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
@@ -1240,16 +1226,11 @@ movntps, 2, 0xf2b, None, 2, CpuSSE, Modr
movntq, 2, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, Qword|Unspecified|BaseIndex }
movntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
movntdq, 2, 0x660fe7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
-movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|BaseIndex }
-movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM }
-movss, 2, 0xf310, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
-movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|RegMem }
-movss, 2, 0xf30f10, None, 2, CpuSSE, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM }
-movups, 2, 0x10, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movups, 2, 0xf10, None, 2, CpuSSE, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movups, 2, 0xf11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM }
+movss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|RegMem, RegXMM }
+movss, 2, 0xf30f10, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
+movups, 2, 0x10, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movups, 2, 0xf10, None, 2, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulss, 2, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -1399,18 +1380,14 @@ minpd, 2, 0x665d, None, 1, CpuAVX, Modrm
minpd, 2, 0x660f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
minsd, 2, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
minsd, 2, 0xf20f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movapd, 2, 0x6628, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movapd, 2, 0x660f28, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movapd, 2, 0x660f29, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movapd, 2, 0x6628, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movapd, 2, 0x660f28, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movhpd, 2, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movhpd, 2, 0x660f16, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movhpd, 2, 0x660f17, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movhpd, 2, 0x660f16, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movlpd, 2, 0x660f12, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-movlpd, 2, 0x660f13, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+movlpd, 2, 0x660f12, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
@@ -1418,16 +1395,11 @@ movntpd, 2, 0x660f2b, None, 2, CpuSSE2,
// Intel mode string move.
movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Unspecified|BaseIndex, Unspecified|BaseIndex|EsSeg }
-movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
-movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
-movsd, 2, 0xf210, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
-movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|Regmem }
-movsd, 2, 0xf20f10, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-movupd, 2, 0x6610, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movupd, 2, 0x660f10, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
+movsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Regmem, RegXMM }
+movsd, 2, 0xf20f10, None, 2, CpuSSE2, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+movupd, 2, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movupd, 2, 0x660f10, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
mulsd, 2, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -1480,14 +1452,10 @@ cvttps2dq, 2, 0xf35b, None, 1, CpuAVX, M
cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
maskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
-movdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movdqa, 2, 0x660f6f, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqa, 2, 0x660f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movdqu, 2, 0xf36f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
-movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|RegXMM }
+movdqa, 2, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movdqa, 2, 0x660f6f, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movdqu, 2, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
+movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX }
movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM }
pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -2037,25 +2005,19 @@ vminpd, 3, 0x665d, None, 1, CpuAVX, Modr
vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vmovapd, 2, 0x6628, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
-vmovaps, 2, 0x28, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
+vmovapd, 2, 0x6628, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vmovaps, 2, 0x28, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
// vmovd really shouldn't allow for 64bit operand (vmovq is the right
// mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated
// by Intel AVX spec). To avoid extra template in gcc x86 backend and
// support assembler for AMD64, we accept 64bit operand on vmovd so
// that we can use one template for both SSE and AVX instructions.
-vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, RegXMM }
-vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
-vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|RegMem }
+vmovd, 2, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
+vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|RegMem, RegXMM }
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
-vmovdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
-vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
+vmovdqa, 2, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vmovdqu, 2, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovhpd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vmovhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
@@ -2074,22 +2036,17 @@ vmovntpd, 2, 0x662b, None, 1, CpuAVX, Mo
vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Qword|Unspecified|BaseIndex, RegXMM }
-vmovq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Qword|Unspecified|BaseIndex }
-vmovsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
-vmovsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
+vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
+vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xf210, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
-vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
+vmovss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
vmovss, 3, 0xf310, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
-vmovupd, 2, 0x6610, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
-vmovups, 2, 0x10, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM }
+vmovupd, 2, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vmovups, 2, 0x10, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -2867,8 +2824,7 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|N

// MPX instructions.
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex, RegBND }
-bndmov, 2, 0x660f1a, None, 2, CpuMPX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
-bndmov, 2, 0x660f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|RegBND }
+bndmov, 2, 0x660f1a, None, 2, CpuMPX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND }
bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
@@ -2907,8 +2863,7 @@ kxorw, 3, 0x47, None, 1, CpuAVX512F, Mod

kmovw, 2, 0x90, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Word|Unspecified|BaseIndex, RegMask }
kmovw, 2, 0x91, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Word|Unspecified|BaseIndex }
-kmovw, 2, 0x92, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
-kmovw, 2, 0x93, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
+kmovw, 2, 0x92, None, 1, CpuAVX512F, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }

knotw, 2, 0x44, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
kortestw, 2, 0x98, None, 1, CpuAVX512F, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -3730,40 +3685,23 @@ vmaxss, 4, 0xF35F, None, 1, CpuAVX512F,
vminss, 3, 0xF35D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
vminss, 4, 0xF35D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }

-vmovapd, 2, 0x6628, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovapd, 2, 0x6629, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
+vmovapd, 2, 0x6628, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovntpd, 2, 0x662B, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
+vmovupd, 2, 0x6610, None, 1, CpuAVX512F, D|Modrm|Load|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

-vmovupd, 2, 0x6610, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovupd, 2, 0x6611, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovaps, 2, 0x28, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovaps, 2, 0x29, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
+vmovaps, 2, 0x28, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovntps, 2, 0x2B, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
+vmovups, 2, 0x10, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

-vmovups, 2, 0x10, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovups, 2, 0x11, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovd, 2, 0x666E, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x667E, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+vmovd, 2, 0x666E, None, 1, CpuAVX512F, D|Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }

vmovddup, 2, 0xF212, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM }

-vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqa64, 2, 0x667F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqa32, 2, 0x667F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
+vmovdqa64, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqa32, 2, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovntdq, 2, 0x66E7, None, 1, CpuAVX512F, Modrm|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
-
-vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu32, 2, 0xF37F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu64, 2, 0xF37F, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
+vmovdqu32, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu64, 2, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

vmovhlps, 3, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovlhps, 3, 0x16, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
@@ -3778,22 +3716,19 @@ vmovhps, 2, 0x17, None, 1, CpuAVX512F, M
vmovlps, 3, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vmovlps, 2, 0x13, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }

-vmovq, 2, 0x666E, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Reg64, RegXMM }
-vmovq, 2, 0x667E, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Reg64 }
+vmovq, 2, 0x666E, None, 1, CpuAVX512F|Cpu64, D|Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovq, 2, 0xF37E, None, 1, CpuAVX512F, Load|Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovq, 2, 0x66D6, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

-vmovsd, 2, 0xF211, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+vmovsd, 2, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xF210, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovsd, 2, 0xF210, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
vmovsd, 3, 0xF211, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }

vmovshdup, 2, 0xF316, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovsldup, 2, 0xF312, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

-vmovss, 2, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
+vmovss, 2, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
vmovss, 3, 0xF310, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovss, 2, 0xF310, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
vmovss, 3, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }

vpabsd, 2, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -4214,6 +4149,7 @@ kandd, 3, 0x6641, None, 1, CpuAVX512BW,
kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
kmovd, 2, 0x6690, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex, RegMask }
kmovd, 2, 0x6691, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspecified|BaseIndex }
+kmovd, 2, 0xF292, None, 1, CpuAVX512BW, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
knotd, 2, 0x6644, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
kord, 3, 0x6645, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kortestd, 2, 0x6698, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -4226,6 +4162,7 @@ kandnq, 3, 0x42, None, 1, CpuAVX512BW, M
kandq, 3, 0x41, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kmovq, 2, 0x90, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex, RegMask }
kmovq, 2, 0x91, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecified|BaseIndex }
+kmovq, 2, 0xF292, None, 1, CpuAVX512BW, D|Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask }
knotq, 2, 0x44, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
korq, 3, 0x45, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kortestq, 2, 0x98, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -4235,11 +4172,6 @@ kunpckwd, 3, 0x4B, None, 1, CpuAVX512BW,
kxnorq, 3, 0x46, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }

-kmovd, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
-kmovd, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
-kmovq, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask }
-kmovq, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg64 }
-
kshiftld, 3, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
kshiftlq, 3, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
kshiftrd, 3, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
@@ -4247,11 +4179,8 @@ kshiftrq, 3, 0x6631, None, 1, CpuAVX512B

vdbpsadbw, 4, 0x6642, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

-vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|Load|Masking=3|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
-
-vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|Load|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
+vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|VexOpcode=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

vpabsb, 2, 0x661C, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vpmaxsb, 3, 0x663C, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
@@ -4418,8 +4347,7 @@ kandb, 3, 0x6641, None, 1, CpuAVX512DQ,
kandnb, 3, 0x6642, None, 1, CpuAVX512DQ, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kmovb, 2, 0x6690, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Byte|Unspecified|BaseIndex, RegMask }
kmovb, 2, 0x6691, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Byte|Unspecified|BaseIndex }
-kmovb, 2, 0x6692, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
-kmovb, 2, 0x6693, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
+kmovb, 2, 0x6692, None, 1, CpuAVX512DQ, D|Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
knotb, 2, 0x6644, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
korb, 3, 0x6645, None, 1, CpuAVX512DQ, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
kortestb, 2, 0x6698, None, 1, CpuAVX512DQ, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
H.J. Lu
2018-09-13 12:57:52 UTC
Permalink
Post by Jan Beulich
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.
Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
gas/
* config/tc-i386.c (operand_size_match): Mirror
.reg/.regsimd/.acc handling from forward to reverse case.
(build_vex_prefix): Check first and last operand types are equal
and also consider .d for swapping operands for VEX2 encoding.
(match_template): Clear found_reverse_match on every iteration.
Use Opcode_SIMD_FloatD and Opcode_SIMD_IntD.
* testsuite/gas/i386/pseudos.s,
testsuite/gas/i386/x86-64-pseudos.s: Add kmov* tests.
* testsuite/gas/i386/pseudos.d,
testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations.
opcodes/
* i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
Fold load and store templates where possible, adding D. Drop
IgnoreSize where it was pointlessly present. Drop redundant
*word.
* i386-tbl.h: Re-generate.
On Linux/x86-64, this caused

FAIL: i386 arch 10
FAIL: i386 arch 10 (lzcnt)
FAIL: i386 arch 10 (prefetchw)
FAIL: i386 arch 10 (bdver1)
FAIL: i386 arch 10 (bdver2)
FAIL: i386 arch 10 (bdver3)
FAIL: i386 arch 10 (bdver4)
FAIL: i386 arch 10 (btver1)
FAIL: i386 arch 10 (btver2)
FAIL: i386 noavx-1
FAIL: i386 noavx-3
FAIL: i386 AVX
FAIL: i386 AVX (Intel disassembly)
FAIL: x86-64 arch 2
FAIL: x86-64 arch 2 (lzcnt)
FAIL: x86-64 arch 2 (prefetchw)
FAIL: x86-64 arch 2 (bdver1)
FAIL: x86-64 arch 2 (bdver2)
FAIL: x86-64 arch 2 (bdver3)
FAIL: x86-64 arch 2 (bdver4)
FAIL: x86-64 arch 2 (btver1)
FAIL: x86-64 arch 2 (btver2)
FAIL: x86-64 AVX
FAIL: x86-64 AVX (Intel mode)

Can you fix it today?
--
H.J.
Jan Beulich
2018-09-05 13:05:38 UTC
Permalink
For now this is just for VMOVS{D,S}.

gas/
2018-09-05 Jan Beulich <***@suse.com>

* config/tc-i386.c (operand_size_match): Also deal with three
operand case.
(match_template): Also allow operand reversal for three operand
templates.

opcodes/
2018-09-05 Jan Beulich <***@suse.com>

* i386-opc.tbl (vmovsd, vmovss): Fold register form load and
store templates, adding D.
* i386-tbl.h: Re-generate.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2053,23 +2053,26 @@ mismatch:
}

/* Check reverse. */
- gas_assert (i.operands == 2);
+ gas_assert (i.operands >= 2 && i.operands <= 3);

- for (j = 0; j < 2; j++)
+ for (j = 0; j < i.operands; j++)
{
+ unsigned int given = i.operands - j - 1;
+
if (t->operand_types[j].bitfield.reg
- && !match_operand_size (t, j, !j))
+ && !match_operand_size (t, j, given))
goto mismatch;

if (t->operand_types[j].bitfield.regsimd
- && !match_simd_size (t, j, !j))
+ && !match_simd_size (t, j, given))
goto mismatch;

if (t->operand_types[j].bitfield.acc
- && (!match_operand_size (t, j, !j) || !match_simd_size (t, j, !j)))
+ && (!match_operand_size (t, j, given)
+ || !match_simd_size (t, j, given)))
goto mismatch;

- if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
+ if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
goto mismatch;
}

@@ -5711,6 +5714,9 @@ match_template (char mnem_suffix)
&& i.types[0].bitfield.acc
&& operand_type_check (i.types[1], anymem))
continue;
+ /* Fall through. */
+
+ case 3:
if (!(size_match & MATCH_STRAIGHT))
goto check_reverse;
/* Reverse direction of operands if swapping is possible in the first
@@ -5719,7 +5725,7 @@ match_template (char mnem_suffix)
- the store form is requested, and the template is a load form,
- the non-default (swapped) form is requested. */
overlap1 = operand_type_and (operand_types[0], operand_types[1]);
- if (t->opcode_modifier.d && i.reg_operands == 2
+ if (t->opcode_modifier.d && i.reg_operands == i.operands
&& !operand_type_all_zero (&overlap1))
switch (i.dir_encoding)
{
@@ -5741,9 +5747,6 @@ match_template (char mnem_suffix)
case dir_encoding_default:
break;
}
- /* Fall through. */
-
- case 3:
/* If we want store form, we skip the current load. */
if ((i.dir_encoding == dir_encoding_store
|| i.dir_encoding == dir_encoding_swap)
@@ -5770,14 +5773,14 @@ check_reverse:
if (!(size_match & MATCH_REVERSE))
continue;
/* Try reversing direction of operands. */
- overlap0 = operand_type_and (i.types[0], operand_types[1]);
- overlap1 = operand_type_and (i.types[1], operand_types[0]);
+ overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
+ overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
if (!operand_type_match (overlap0, i.types[0])
- || !operand_type_match (overlap1, i.types[1])
+ || !operand_type_match (overlap1, i.types[i.operands - 1])
|| (check_register
&& !operand_type_register_match (i.types[0],
- operand_types[1],
- i.types[1],
+ operand_types[i.operands - 1],
+ i.types[i.operands - 1],
operand_types[0])))
{
/* Does not match either direction. */
@@ -5790,9 +5793,9 @@ check_reverse:
else if (operand_types[0].bitfield.tbyte)
found_reverse_match = Opcode_FloatD;
else if (operand_types[0].bitfield.xmmword
- || operand_types[1].bitfield.xmmword
+ || operand_types[i.operands - 1].bitfield.xmmword
|| operand_types[0].bitfield.regmmx
- || operand_types[1].bitfield.regmmx
+ || operand_types[i.operands - 1].bitfield.regmmx
|| is_any_vex_encoding(t))
found_reverse_match = (t->base_opcode & 0xee) != 0x6e
? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
@@ -5990,8 +5993,8 @@ check_reverse:

i.tm.base_opcode ^= found_reverse_match;

- i.tm.operand_types[0] = operand_types[1];
- i.tm.operand_types[1] = operand_types[0];
+ i.tm.operand_types[0] = operand_types[i.operands - 1];
+ i.tm.operand_types[i.operands - 1] = operand_types[0];
}

return t;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2038,13 +2038,11 @@ vmovq, 2, 0xf37e, None, 1, CpuAVX, Load|
vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovsd, 2, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-vmovsd, 3, 0xf210, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovsd, 3, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }
vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovss, 2, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
-vmovss, 3, 0xf310, None, 1, CpuAVX, Load|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovss, 3, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }
vmovupd, 2, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmovups, 2, 0x10, None, 1, CpuAVX, D|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -3721,15 +3719,13 @@ vmovq, 2, 0xF37E, None, 1, CpuAVX512F, L
vmovq, 2, 0x66D6, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }

vmovsd, 2, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-vmovsd, 3, 0xF210, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovsd, 3, 0xF211, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovsd, 3, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

vmovshdup, 2, 0xF316, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vmovsldup, 2, 0xF312, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }

vmovss, 2, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
-vmovss, 3, 0xF310, None, 1, CpuAVX512F, Modrm|Load|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
-vmovss, 3, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem }
+vmovss, 3, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegMem, RegXMM, RegXMM }

vpabsd, 2, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vrcp14ps, 2, 0x664C, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
Jan Beulich
2018-09-05 13:06:06 UTC
Permalink
opcodes/
2018-09-05 Jan Beulich <***@suse.com>

* i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
(vpbroadcastw, rdpid): Drop NoRex64.
* i386-tbl.h: Re-generate.

--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1733,7 +1733,7 @@ pcmpistrm, 3, 0x660f3a62, None, 3, CpuSS
// We put non-8bit version before 8bit so that crc32 with memory operand
// defaults to non-8bit.
crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex, Reg32 }
-crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64|NoAVX, { Reg64|Qword|Unspecified|BaseIndex, Reg64 }
+crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoAVX, { Reg64|Qword|Unspecified|BaseIndex, Reg64 }
crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg8|Byte|Unspecified|BaseIndex, Reg32 }
crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }

@@ -4245,7 +4245,7 @@ vpsravw, 3, 0x6611, None, 1, CpuAVX512BW
vpsrlvw, 3, 0x6610, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

vpbroadcastw, 2, 0x6679, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegXMM|RegYMM|RegZMM }
+vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM }

vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
@@ -4626,7 +4626,7 @@ wrpkru, 0, 0xf01ef, None, 3, CpuOSPKE, N

// RDPID instructions.

-rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32 }
+rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }

// RDPID instructions end.
@@ -4640,9 +4640,9 @@ ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE
// CET instructions.

incsspd, 1, 0xf30fae, 0x5, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-incsspq, 1, 0xf30fae, 0x5, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
+incsspq, 1, 0xf30fae, 0x5, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64 }
rdsspd, 1, 0xf30f1e, 0x1, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-rdsspq, 1, 0xf30f1e, 0x1, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
+rdsspq, 1, 0xf30f1e, 0x1, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64 }
saveprevssp, 0, 0xf30f01ea, None, 3, CpuSHSTK, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
rstorssp, 1, 0xf30f01, 0x5, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
wrssd, 2, 0x0f38f6, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex }
H.J. Lu
2018-09-12 21:19:16 UTC
Permalink
Post by Jan Beulich
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64
Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.
All looks good, except for

https://sourceware.org/ml/binutils/2018-09/msg00026.html

Please don't add new tests with the .s suffix. Please use {load} or
{store} instead.
If it isn't appropriate for x87 insns, we can skip them.
--
H.J.
Jan Beulich
2018-09-13 08:59:31 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64
Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.
All looks good, except for
https://sourceware.org/ml/binutils/2018-09/msg00026.html
Please don't add new tests with the .s suffix. Please use {load} or
{store} instead.
That's done in the earlier patch. I did submit the split parts in order
to have everything available, but I'll simply omit that patch when
committing (I take your response as "okay except for this one patch").

Jan
H.J. Lu
2018-09-13 11:58:05 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64
Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.
All looks good, except for
https://sourceware.org/ml/binutils/2018-09/msg00026.html
Please don't add new tests with the .s suffix. Please use {load} or
{store} instead.
That's done in the earlier patch. I did submit the split parts in order
to have everything available, but I'll simply omit that patch when
committing (I take your response as "okay except for this one patch").
That is OK.

Thanks.
--
H.J.
H.J. Lu
2018-09-13 12:48:38 UTC
Permalink
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64
Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.
All looks good, except for
https://sourceware.org/ml/binutils/2018-09/msg00026.html
Please don't add new tests with the .s suffix. Please use {load} or
{store} instead.
That's done in the earlier patch. I did submit the split parts in order
to have everything available, but I'll simply omit that patch when
committing (I take your response as "okay except for this one patch").
That is OK.
Thanks.
--
H.J.
But I see:

FAIL: i386 arch 10
FAIL: i386 arch 10 (lzcnt)
FAIL: i386 arch 10 (prefetchw)
FAIL: i386 arch 10 (bdver1)
FAIL: i386 arch 10 (bdver2)
FAIL: i386 arch 10 (bdver3)
FAIL: i386 arch 10 (bdver4)
FAIL: i386 arch 10 (btver1)
FAIL: i386 arch 10 (btver2)
FAIL: i386 noavx-1
FAIL: i386 noavx-3
FAIL: i386 AVX
FAIL: i386 AVX (Intel disassembly)
FAIL: x86-64 arch 2
FAIL: x86-64 arch 2 (lzcnt)
FAIL: x86-64 arch 2 (prefetchw)
FAIL: x86-64 arch 2 (bdver1)
FAIL: x86-64 arch 2 (bdver2)
FAIL: x86-64 arch 2 (bdver3)
FAIL: x86-64 arch 2 (bdver4)
FAIL: x86-64 arch 2 (btver1)
FAIL: x86-64 arch 2 (btver2)
FAIL: x86-64 AVX
FAIL: x86-64 AVX (Intel mode)
FAIL: x86-64 (ILP32) arch 2
FAIL: x86-64 (ILP32) AVX (Intel mode)
FAIL: x86-64 (ILP32) AVX
--
H.J.
Jan Beulich
2018-09-13 12:55:06 UTC
Permalink
Post by H.J. Lu
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64
Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.
All looks good, except for
https://sourceware.org/ml/binutils/2018-09/msg00026.html
Please don't add new tests with the .s suffix. Please use {load} or
{store} instead.
That's done in the earlier patch. I did submit the split parts in order
to have everything available, but I'll simply omit that patch when
committing (I take your response as "okay except for this one patch").
That is OK.
Thanks.
--
H.J.
FAIL: i386 arch 10
FAIL: i386 arch 10 (lzcnt)
FAIL: i386 arch 10 (prefetchw)
FAIL: i386 arch 10 (bdver1)
FAIL: i386 arch 10 (bdver2)
FAIL: i386 arch 10 (bdver3)
FAIL: i386 arch 10 (bdver4)
FAIL: i386 arch 10 (btver1)
FAIL: i386 arch 10 (btver2)
FAIL: i386 noavx-1
FAIL: i386 noavx-3
FAIL: i386 AVX
FAIL: i386 AVX (Intel disassembly)
FAIL: x86-64 arch 2
FAIL: x86-64 arch 2 (lzcnt)
FAIL: x86-64 arch 2 (prefetchw)
FAIL: x86-64 arch 2 (bdver1)
FAIL: x86-64 arch 2 (bdver2)
FAIL: x86-64 arch 2 (bdver3)
FAIL: x86-64 arch 2 (bdver4)
FAIL: x86-64 arch 2 (btver1)
FAIL: x86-64 arch 2 (btver2)
FAIL: x86-64 AVX
FAIL: x86-64 AVX (Intel mode)
FAIL: x86-64 (ILP32) arch 2
FAIL: x86-64 (ILP32) AVX (Intel mode)
FAIL: x86-64 (ILP32) AVX
For which target(s)? The testsuite certainly ran without any regressions
for me, at every patch boundary.

Jan
H.J. Lu
2018-09-13 13:19:59 UTC
Permalink
Post by Jan Beulich
Post by H.J. Lu
Post by H.J. Lu
Post by Jan Beulich
Post by H.J. Lu
Post by Jan Beulich
1: add code comment on deprecated status of pseudo-suffixes
2: improve operand reversal
3: fold ILP32 output of "opts" tests
4: extra operand reversal "opts" tests
5: use D attribute also for SIMD templates
6: also allow D on 3-operand insns
7: drop unnecessary {,No}Rex64
Besides the new last patch the main change here compared to v1 is
the splitting up of what is now patch 2. Patches 3 and 4 are therefore
optional now. Patches 5 and 6 have been approved already, but
can't go in without what is now patch 2.
All looks good, except for
https://sourceware.org/ml/binutils/2018-09/msg00026.html
Please don't add new tests with the .s suffix. Please use {load} or
{store} instead.
That's done in the earlier patch. I did submit the split parts in order
to have everything available, but I'll simply omit that patch when
committing (I take your response as "okay except for this one patch").
That is OK.
Thanks.
--
H.J.
FAIL: i386 arch 10
FAIL: i386 arch 10 (lzcnt)
FAIL: i386 arch 10 (prefetchw)
FAIL: i386 arch 10 (bdver1)
FAIL: i386 arch 10 (bdver2)
FAIL: i386 arch 10 (bdver3)
FAIL: i386 arch 10 (bdver4)
FAIL: i386 arch 10 (btver1)
FAIL: i386 arch 10 (btver2)
FAIL: i386 noavx-1
FAIL: i386 noavx-3
FAIL: i386 AVX
FAIL: i386 AVX (Intel disassembly)
FAIL: x86-64 arch 2
FAIL: x86-64 arch 2 (lzcnt)
FAIL: x86-64 arch 2 (prefetchw)
FAIL: x86-64 arch 2 (bdver1)
FAIL: x86-64 arch 2 (bdver2)
FAIL: x86-64 arch 2 (bdver3)
FAIL: x86-64 arch 2 (bdver4)
FAIL: x86-64 arch 2 (btver1)
FAIL: x86-64 arch 2 (btver2)
FAIL: x86-64 AVX
FAIL: x86-64 AVX (Intel mode)
FAIL: x86-64 (ILP32) arch 2
FAIL: x86-64 (ILP32) AVX (Intel mode)
FAIL: x86-64 (ILP32) AVX
For which target(s)? The testsuite certainly ran without any regressions
for me, at every patch boundary.
it failed on "zveroall". I checked in a fix.
--
H.J.
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