[PATCH 0/2] x86: Update support for VEX WIG instructions

[H.J. Lu]

The VEX.Wbit is ignored by some VEX instructions, aka WIG instructions.
This patch set does

1. Update disassembler for WIG VEX instructions.
2. Add -mvexwig=[0|1] assembler option to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.

H.J. Lu (2):
x86: Update disassembler for VexWIG
x86: Add -mvexwig=[0|1] option to assembler

gas/NEWS | 3 +
gas/config/tc-i386.c | 45 +-
gas/doc/c-i386.texi | 10 +
gas/testsuite/gas/i386/avx-wig.d | 254 +++
gas/testsuite/gas/i386/avx-wig.s | 248 +++
gas/testsuite/gas/i386/avx2-wig.d | 119 ++
gas/testsuite/gas/i386/avx2-wig.s | 113 ++
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/x86-64-avx-wig.d | 256 +++
gas/testsuite/gas/i386/x86-64-avx-wig.s | 250 +++
gas/testsuite/gas/i386/x86-64-avx2-wig.d | 119 ++
gas/testsuite/gas/i386/x86-64-avx2-wig.s | 113 ++
opcodes/i386-dis.c | 1987 ++++------------------
13 files changed, 1851 insertions(+), 1670 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-wig.d
create mode 100644 gas/testsuite/gas/i386/avx-wig.s
create mode 100644 gas/testsuite/gas/i386/avx2-wig.d
create mode 100644 gas/testsuite/gas/i386/avx2-wig.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-wig.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-wig.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx2-wig.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx2-wig.s

[H.J. Lu]

Add -mvexwig=[0|1] option to x86 assembler to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.

* gas/NEWS: Mention -mvexwig=[0|1] option.
* config/tc-i386.c (vexwig): New.
(build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG
VEX instructions.
(OPTION_MVEXWIG): New.
(md_longopts): Add -mvexwig=.
(md_parse_option): Handle OPTION_MVEXWIG.
(md_show_usage): Show -mvexwig=[0|1].
* doc/c-i386.texi: Document -mvexwig=[0|1].
* testsuite/gas/i386/avx-wig.d: New file.
* testsuite/gas/i386/avx-wig.s: Likewise.
* testsuite/gas/i386/avx2-wig.d: Likewise.
* testsuite/gas/i386/avx2-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.s: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig,
x86-64-avx-wig and x86-64-avx2-wig.
---
gas/NEWS | 3 +
gas/config/tc-i386.c | 45 +++-
gas/doc/c-i386.texi | 10 +
gas/testsuite/gas/i386/avx-wig.d | 254 ++++++++++++++++++++++
gas/testsuite/gas/i386/avx-wig.s | 248 ++++++++++++++++++++++
gas/testsuite/gas/i386/avx2-wig.d | 119 +++++++++++
gas/testsuite/gas/i386/avx2-wig.s | 113 ++++++++++
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/x86-64-avx-wig.d | 256 +++++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-avx-wig.s | 250 ++++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-avx2-wig.d | 119 +++++++++++
gas/testsuite/gas/i386/x86-64-avx2-wig.s | 113 ++++++++++
12 files changed, 1523 insertions(+), 11 deletions(-)
create mode 100644 gas/testsuite/gas/i386/avx-wig.d
create mode 100644 gas/testsuite/gas/i386/avx-wig.s
create mode 100644 gas/testsuite/gas/i386/avx2-wig.d
create mode 100644 gas/testsuite/gas/i386/avx2-wig.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-wig.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx-wig.s
create mode 100644 gas/testsuite/gas/i386/x86-64-avx2-wig.d
create mode 100644 gas/testsuite/gas/i386/x86-64-avx2-wig.s

diff --git a/gas/NEWS b/gas/NEWS
index 87fe10a474..26f78b08c6 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
-*- text -*-

+* Add -mvexwig=[0|1] option to x86 assembler to control encoding of
+ VEX.W-ignored (WIG) VEX instructions.
+
* Add -mx86-used-note=[yes|no] option to generate (or not) x86 GNU property
notes. Add a --enable-x86-used-note configure time option to set the
default behavior. Set the default if the configure option is not used
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d2ee3b4445..2204d00d8c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -684,6 +684,13 @@ static enum
vex256
} avxscalar;

+/* Encode VEX WIG instructions with specific vex.w. */
+static enum
+ {
+ vexw0 = 0,
+ vexw1
+ } vexwig;
+
/* Encode scalar EVEX LIG instructions with specific vector length. */
static enum
{
@@ -3353,6 +3360,7 @@ build_vex_prefix (const insn_template *t)
unsigned int register_specifier;
unsigned int implied_prefix;
unsigned int vector_length;
+ unsigned int w;

/* Check register specifier. */
if (i.vex.register_specifier)
@@ -3439,10 +3447,18 @@ build_vex_prefix (const insn_template *t)
abort ();
}

+ /* Check the REX.W bit and VEXW. */
+ if (i.tm.opcode_modifier.vexw == VEXWIG)
+ w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
+ else if (i.tm.opcode_modifier.vexw)
+ w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
+ else
+ w = (i.rex & REX_W) ? 1 : 0;
+
/* Use 2-byte VEX prefix if possible. */
- if (i.vec_encoding != vex_encoding_vex3
+ if (w == 0
+ && i.vec_encoding != vex_encoding_vex3
&& i.tm.opcode_modifier.vexopcode == VEX0F
- && i.tm.opcode_modifier.vexw != VEXW1
&& (i.rex & (REX_W | REX_X | REX_B)) == 0)
{
/* 2-byte VEX prefix. */
@@ -3461,7 +3477,7 @@ build_vex_prefix (const insn_template *t)
else
{
/* 3-byte VEX prefix. */
- unsigned int m, w;
+ unsigned int m;

i.vex.length = 3;

@@ -3499,14 +3515,6 @@ build_vex_prefix (const insn_template *t)
of RXB bits from REX. */
i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;

- /* Check the REX.W bit and VEXW. */
- if (i.tm.opcode_modifier.vexw == VEXWIG)
- w = (i.rex & REX_W) ? 1 : 0;
- else if (i.tm.opcode_modifier.vexw)
- w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
- else
- w = (i.rex & REX_W) ? 1 : 0;
-
i.vex.bytes[2] = (w << 7
| register_specifier << 3
| vector_length << 2
@@ -10878,6 +10886,7 @@ const char *md_shortopts = "qnO::";
#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
#define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
+#define OPTION_MVEXWIG (OPTION_MD_BASE + 26)

struct option md_longopts[] =
{
@@ -10902,6 +10911,7 @@ struct option md_longopts[] =
{"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
{"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
{"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
+ {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
{"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
{"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
{"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
@@ -11219,6 +11229,15 @@ md_parse_option (int c, const char *arg)
as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
break;

+ case OPTION_MVEXWIG:
+ if (strcmp (arg, "0") == 0)
+ vexwig = evexw0;
+ else if (strcmp (arg, "1") == 0)
+ vexwig = evexw1;
+ else
+ as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
+ break;
+
case OPTION_MADD_BND_PREFIX:
add_bnd_prefix = 1;
break;
@@ -11477,6 +11496,10 @@ md_show_usage (FILE *stream)
encode scalar AVX instructions with specific vector\n\
length\n"));
fprintf (stream, _("\
+ -mvexwig=[0|1] (default: 0)\n\
+ encode VEX instructions with specific VEX.W value\n\
+ for VEX.W bit ignored instructions\n"));
+ fprintf (stream, _("\
-mevexlig=[128|256|512] (default: 128)\n\
encode scalar EVEX instructions with specific vector\n\
length\n"));
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 64e33977d7..77ccfbc1ab 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -298,6 +298,16 @@ AVX instructions with 128bit vector length, which is the default.
@option{-mavxscalar=@var{256}} will encode scalar AVX instructions
with 256bit vector length.

+@cindex @samp{-mvexwig=} option, i386
+@cindex @samp{-mvexwig=} option, x86-64
+@item -mvexwig=@var{0}
+@itemx -mvexwig=@var{1}
+These options control how the assembler should encode VEX.W-ignored (WIG)
+VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
+instructions with vex.w = 0, which is the default.
+@option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
+vex.w = 1.
+
@cindex @samp{-mevexlig=} option, i386
@cindex @samp{-mevexlig=} option, x86-64
@item -mevexlig=@var{128}
diff --git a/gas/testsuite/gas/i386/avx-wig.d b/gas/testsuite/gas/i386/avx-wig.d
new file mode 100644
index 0000000000..00a2195917
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-wig.d
@@ -0,0 +1,254 @@
+#as: -mvexwig=1
+#objdump: -dw
+#name: i386 AVX WIG insns with -mvexwig=1
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c4 e1 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd d0 d4 vaddsubpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cf d0 d4 vaddsubps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 c9 de d4 vaesdec %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 df d4 vaesdeclast %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 dc d4 vaesenc %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 dd d4 vaesenclast %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 f9 db f4 vaesimc %xmm4,%xmm6
+ +[a-f0-9]+: c4 e3 f9 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e3 cd 0d d4 07 vblendpd \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 cd 0c d4 07 vblendps \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 2f f4 vcomisd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 2f f4 vcomiss %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fe e6 e4 vcvtdq2pd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e1 fc 5b f4 vcvtdq2ps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fb e6 f4 vcvtpd2dq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 f9 5a f4 vcvtpd2ps %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fd 5b f4 vcvtps2dq %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 5a e4 vcvtps2pd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e1 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fe 5b f4 vcvttps2dq %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 cd 5e d4 vdivpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5e d4 vdivps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5e d4 vdivsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 cd 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 f9 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cf 7d d4 vhsubps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 c9 21 d4 07 vinsertps \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ff f0 21 vlddqu \(%ecx\),%ymm4
+ +[a-f0-9]+: c4 e1 f8 ae 11 vldmxcsr \(%ecx\)
+ +[a-f0-9]+: c4 e1 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 cd 5f d4 vmaxpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5f d4 vmaxps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5f d4 vmaxsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5f d4 vmaxss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd 5d d4 vminpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5d d4 vminps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5d d4 vminsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5d d4 vminss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fd 28 f4 vmovapd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 28 f4 vmovaps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 29 e6 vmovapd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 29 e6 vmovaps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ff 12 f4 vmovddup %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 6f f4 vmovdqa %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fe 6f f4 vmovdqu %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 7f e6 vmovdqa %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fe 7f e6 vmovdqu %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 c8 12 d4 vmovhlps %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 d9 16 31 vmovhpd \(%ecx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f9 17 21 vmovhpd %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 d8 16 31 vmovhps \(%ecx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 17 21 vmovhps %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 d9 12 31 vmovlpd \(%ecx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f9 13 21 vmovlpd %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 d8 12 31 vmovlps \(%ecx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 13 21 vmovlps %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 f9 50 cc vmovmskpd %xmm4,%ecx
+ +[a-f0-9]+: c4 e1 f8 50 cc vmovmskps %xmm4,%ecx
+ +[a-f0-9]+: c4 e1 fd e7 21 vmovntdq %ymm4,\(%ecx\)
+ +[a-f0-9]+: c4 e2 f9 2a 21 vmovntdqa \(%ecx\),%xmm4
+ +[a-f0-9]+: c4 e1 fd 2b 21 vmovntpd %ymm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 fc 2b 21 vmovntps %ymm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 fa 7e f4 vmovq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f9 d6 21 vmovq %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 fb 10 21 vmovsd \(%ecx\),%xmm4
+ +[a-f0-9]+: c4 e1 fb 11 21 vmovsd %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 fe 16 f4 vmovshdup %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fe 12 f4 vmovsldup %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fa 10 21 vmovss \(%ecx\),%xmm4
+ +[a-f0-9]+: c4 e1 fa 11 21 vmovss %xmm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 fd 10 f4 vmovupd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 11 21 vmovupd %ymm4,\(%ecx\)
+ +[a-f0-9]+: c4 e1 fc 10 f4 vmovups %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 11 21 vmovups %ymm4,\(%ecx\)
+ +[a-f0-9]+: c4 e3 c9 42 d4 07 vmpsadbw \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd 59 d4 vmulpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 59 d4 vmulps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 59 d4 vmulsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 59 d4 vmulss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 f9 1c f4 vpabsb %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 1e f4 vpabsd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 1d f4 vpabsw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 c9 6b d4 vpackssdw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 63 d4 vpacksswb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 2b d4 vpackusdw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 67 d4 vpackuswb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fc d4 vpaddb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fe d4 vpaddd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d4 d4 vpaddq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ec d4 vpaddsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ed d4 vpaddsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 dc d4 vpaddusb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 dd d4 vpaddusw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fd d4 vpaddw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 0f d4 07 vpalignr \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 db d4 vpand %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 df d4 vpandn %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e0 d4 vpavgb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e3 d4 vpavgw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 0e d4 07 vpblendw \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 11 vpclmulhqhqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 01 vpclmulhqlqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 10 vpclmullqhqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 00 vpclmullqlqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 07 vpclmulqdq \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 74 d4 vpcmpeqb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 76 d4 vpcmpeqd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 29 d4 vpcmpeqq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 75 d4 vpcmpeqw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 64 d4 vpcmpgtb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 66 d4 vpcmpgtd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 37 d4 vpcmpgtq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 f9 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e3 f9 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 02 d4 vphaddd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 03 d4 vphaddsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 01 d4 vphaddw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 f9 41 f4 vphminposuw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 06 d4 vphsubd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 07 d4 vphsubsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 05 d4 vphsubw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3d d4 vpmaxsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ee d4 vpmaxsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c5 c9 de d4 vpmaxub %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3f d4 vpmaxud %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3e d4 vpmaxuw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 38 d4 vpminsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 39 d4 vpminsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ea d4 vpminsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 da d4 vpminub %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3b d4 vpminud %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3a d4 vpminuw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 d7 cc vpmovmskb %xmm4,%ecx
+ +[a-f0-9]+: c4 e2 f9 21 f4 vpmovsxbd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 22 f4 vpmovsxbq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 20 f4 vpmovsxbw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 25 f4 vpmovsxdq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 23 f4 vpmovsxwd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 24 f4 vpmovsxwq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 31 f4 vpmovzxbd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 32 f4 vpmovzxbq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 30 f4 vpmovzxbw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 35 f4 vpmovzxdq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 33 f4 vpmovzxwd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 34 f4 vpmovzxwq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 28 d4 vpmuldq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 0b d4 vpmulhrsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e4 d4 vpmulhuw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e5 d4 vpmulhw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 40 d4 vpmulld %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d5 d4 vpmullw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f4 d4 vpmuludq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 eb d4 vpor %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f6 d4 vpsadbw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 00 d4 vpshufb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 70 f4 07 vpshufd \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fa 70 f4 07 vpshufhw \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fb 70 f4 07 vpshuflw \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 08 d4 vpsignb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 0a d4 vpsignd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 09 d4 vpsignw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f2 d4 vpslld %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 73 fc 07 vpslldq \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 c9 f3 d4 vpsllq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f1 d4 vpsllw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e2 d4 vpsrad %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e1 d4 vpsraw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d2 d4 vpsrld %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 73 dc 07 vpsrldq \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 c9 d3 d4 vpsrlq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d1 d4 vpsrlw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f8 d4 vpsubb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fa d4 vpsubd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fb d4 vpsubq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e8 d4 vpsubsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e9 d4 vpsubsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d8 d4 vpsubusb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d9 d4 vpsubusw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f9 d4 vpsubw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 fd 17 f4 vptest %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 c9 68 d4 vpunpckhbw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 6a d4 vpunpckhdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 6d d4 vpunpckhqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 69 d4 vpunpckhwd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 60 d4 vpunpcklbw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 62 d4 vpunpckldq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 6c d4 vpunpcklqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 61 d4 vpunpcklwd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ef d4 vpxor %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fc 53 f4 vrcpps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ca 53 d4 vrcpss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 fd 09 d6 07 vroundpd \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 fd 08 d6 07 vroundps \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 c9 0b d4 07 vroundsd \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fc 52 f4 vrsqrtps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ca 52 d4 vrsqrtss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd c6 d4 07 vshufpd \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fd 51 f4 vsqrtpd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 51 f4 vsqrtps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 cb 51 d4 vsqrtsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 51 d4 vsqrtss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f8 ae 19 vstmxcsr \(%ecx\)
+ +[a-f0-9]+: c4 e1 cd 5c d4 vsubpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5c d4 vsubps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5c d4 vsubsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5c d4 vsubss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 2e f4 vucomisd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 2e f4 vucomiss %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 cd 15 d4 vunpckhpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 15 d4 vunpckhps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 14 d4 vunpcklpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 14 d4 vunpcklps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 57 d4 vxorpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 57 d4 vxorps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fc 77 vzeroall
+ +[a-f0-9]+: c4 e1 f8 77 vzeroupper
+#pass
diff --git a/gas/testsuite/gas/i386/avx-wig.s b/gas/testsuite/gas/i386/avx-wig.s
new file mode 100644
index 0000000000..fa982368f8
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-wig.s
@@ -0,0 +1,248 @@
+# Check AVX WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vaddpd %ymm4,%ymm6,%ymm2
+ vaddps %ymm4,%ymm6,%ymm2
+ vaddsd %xmm4,%xmm6,%xmm2
+ vaddss %xmm4,%xmm6,%xmm2
+ vaddsubpd %ymm4,%ymm6,%ymm2
+ vaddsubps %ymm4,%ymm6,%ymm2
+ vaesdec %xmm4,%xmm6,%xmm2
+ vaesdeclast %xmm4,%xmm6,%xmm2
+ vaesenc %xmm4,%xmm6,%xmm2
+ vaesenclast %xmm4,%xmm6,%xmm2
+ vaesimc %xmm4,%xmm6
+ vaeskeygenassist $7,%xmm4,%xmm6
+ vblendpd $7,%ymm4,%ymm6,%ymm2
+ vblendps $7,%ymm4,%ymm6,%ymm2
+ vcmppd $7,%ymm4,%ymm6,%ymm2
+ vcmpps $7,%ymm4,%ymm6,%ymm2
+ vcmpsd $7,%xmm4,%xmm6,%xmm2
+ vcmpss $7,%xmm4,%xmm6,%xmm2
+ vcomisd %xmm4,%xmm6
+ vcomiss %xmm4,%xmm6
+ vcvtdq2pd %xmm4,%ymm4
+ vcvtdq2ps %ymm4,%ymm6
+ vcvtpd2dqy %ymm4,%xmm4
+ vcvtpd2dqx %xmm4,%xmm6
+ vcvtpd2dqy %ymm4,%xmm4
+ vcvtpd2psy %ymm4,%xmm4
+ vcvtpd2psx %xmm4,%xmm6
+ vcvtpd2psy %ymm4,%xmm4
+ vcvtps2dq %ymm4,%ymm6
+ vcvtps2pd %xmm4,%ymm4
+ vcvtsd2ss %xmm4,%xmm6,%xmm2
+ vcvttpd2dqy %ymm4,%xmm4
+ vcvttpd2dqx %xmm4,%xmm6
+ vcvttpd2dqy %ymm4,%xmm4
+ vcvttps2dq %ymm4,%ymm6
+ vdivpd %ymm4,%ymm6,%ymm2
+ vdivps %ymm4,%ymm6,%ymm2
+ vdivsd %xmm4,%xmm6,%xmm2
+ vdivss %xmm4,%xmm6,%xmm2
+ vdppd $7,%xmm4,%xmm6,%xmm2
+ vdpps $7,%ymm4,%ymm6,%ymm2
+ vextractps $7,%xmm4,(%ecx)
+ vhaddpd %ymm4,%ymm6,%ymm2
+ vhaddps %ymm4,%ymm6,%ymm2
+ vhsubpd %ymm4,%ymm6,%ymm2
+ vhsubps %ymm4,%ymm6,%ymm2
+ vinsertps $7,%xmm4,%xmm6,%xmm2
+ vlddqu (%ecx),%ymm4
+ vldmxcsr (%ecx)
+ vmaskmovdqu %xmm4,%xmm6
+ vmaxpd %ymm4,%ymm6,%ymm2
+ vmaxps %ymm4,%ymm6,%ymm2
+ vmaxsd %xmm4,%xmm6,%xmm2
+ vmaxss %xmm4,%xmm6,%xmm2
+ vminpd %ymm4,%ymm6,%ymm2
+ vminps %ymm4,%ymm6,%ymm2
+ vminsd %xmm4,%xmm6,%xmm2
+ vminss %xmm4,%xmm6,%xmm2
+ vmovapd %ymm4,%ymm6
+ vmovaps %ymm4,%ymm6
+ {store} vmovapd %ymm4,%ymm6
+ {store} vmovaps %ymm4,%ymm6
+ vmovddup %ymm4,%ymm6
+ vmovdqa %ymm4,%ymm6
+ vmovdqu %ymm4,%ymm6
+ {store} vmovdqa %ymm4,%ymm6
+ {store} vmovdqu %ymm4,%ymm6
+ vmovhlps %xmm4,%xmm6,%xmm2
+ vmovhpd (%ecx),%xmm4,%xmm6
+ vmovhpd %xmm4,(%ecx)
+ vmovhps (%ecx),%xmm4,%xmm6
+ vmovhps %xmm4,(%ecx)
+ vmovlhps %xmm4,%xmm6,%xmm2
+ vmovlpd (%ecx),%xmm4,%xmm6
+ vmovlpd %xmm4,(%ecx)
+ vmovlps (%ecx),%xmm4,%xmm6
+ vmovlps %xmm4,(%ecx)
+ vmovmskpd %xmm4,%ecx
+ vmovmskps %xmm4,%ecx
+ vmovntdq %ymm4,(%ecx)
+ vmovntdqa (%ecx),%xmm4
+ vmovntpd %ymm4,(%ecx)
+ vmovntps %ymm4,(%ecx)
+ vmovq %xmm4,%xmm6
+ vmovq %xmm4,(%ecx)
+ vmovsd (%ecx),%xmm4
+ vmovsd %xmm4,(%ecx)
+ vmovshdup %ymm4,%ymm6
+ vmovsldup %ymm4,%ymm6
+ vmovss (%ecx),%xmm4
+ vmovss %xmm4,(%ecx)
+ vmovupd %ymm4,%ymm6
+ vmovupd %ymm4,(%ecx)
+ vmovups %ymm4,%ymm6
+ vmovups %ymm4,(%ecx)
+ vmpsadbw $7,%xmm4,%xmm6,%xmm2
+ vmulpd %ymm4,%ymm6,%ymm2
+ vmulps %ymm4,%ymm6,%ymm2
+ vmulsd %xmm4,%xmm6,%xmm2
+ vmulss %xmm4,%xmm6,%xmm2
+ vpabsb %xmm4,%xmm6
+ vpabsd %xmm4,%xmm6
+ vpabsw %xmm4,%xmm6
+ vpackssdw %xmm4,%xmm6,%xmm2
+ vpacksswb %xmm4,%xmm6,%xmm2
+ vpackusdw %xmm4,%xmm6,%xmm2
+ vpackuswb %xmm4,%xmm6,%xmm2
+ vpaddb %xmm4,%xmm6,%xmm2
+ vpaddd %xmm4,%xmm6,%xmm2
+ vpaddq %xmm4,%xmm6,%xmm2
+ vpaddsb %xmm4,%xmm6,%xmm2
+ vpaddsw %xmm4,%xmm6,%xmm2
+ vpaddusb %xmm4,%xmm6,%xmm2
+ vpaddusw %xmm4,%xmm6,%xmm2
+ vpaddw %xmm4,%xmm6,%xmm2
+ vpalignr $7,%xmm4,%xmm6,%xmm2
+ vpand %xmm4,%xmm6,%xmm2
+ vpandn %xmm4,%xmm6,%xmm2
+ vpavgb %xmm4,%xmm6,%xmm2
+ vpavgw %xmm4,%xmm6,%xmm2
+ vpblendw $7,%xmm4,%xmm6,%xmm2
+ vpclmulhqhqdq %xmm4,%xmm6,%xmm2
+ vpclmulhqlqdq %xmm4,%xmm6,%xmm2
+ vpclmullqhqdq %xmm4,%xmm6,%xmm2
+ vpclmullqlqdq %xmm4,%xmm6,%xmm2
+ vpclmulqdq $7,%xmm4,%xmm6,%xmm2
+ vpcmpeqb %xmm4,%xmm6,%xmm2
+ vpcmpeqd %xmm4,%xmm6,%xmm2
+ vpcmpeqq %xmm4,%xmm6,%xmm2
+ vpcmpeqw %xmm4,%xmm6,%xmm2
+ vpcmpgtb %xmm4,%xmm6,%xmm2
+ vpcmpgtd %xmm4,%xmm6,%xmm2
+ vpcmpgtq %xmm4,%xmm6,%xmm2
+ vpcmpgtw %xmm4,%xmm6,%xmm2
+ vpcmpistri $7,%xmm4,%xmm6
+ vpcmpistrm $7,%xmm4,%xmm6
+ vphaddd %xmm4,%xmm6,%xmm2
+ vphaddsw %xmm4,%xmm6,%xmm2
+ vphaddw %xmm4,%xmm6,%xmm2
+ vphminposuw %xmm4,%xmm6
+ vphsubd %xmm4,%xmm6,%xmm2
+ vphsubsw %xmm4,%xmm6,%xmm2
+ vphsubw %xmm4,%xmm6,%xmm2
+ vpmaddubsw %xmm4,%xmm6,%xmm2
+ vpmaddwd %xmm4,%xmm6,%xmm2
+ vpmaxsb %xmm4,%xmm6,%xmm2
+ vpmaxsd %xmm4,%xmm6,%xmm2
+ vpmaxsw %xmm4,%xmm6,%xmm2
+ vpmaxub %xmm4,%xmm6,%xmm2
+ vpmaxud %xmm4,%xmm6,%xmm2
+ vpmaxuw %xmm4,%xmm6,%xmm2
+ vpminsb %xmm4,%xmm6,%xmm2
+ vpminsd %xmm4,%xmm6,%xmm2
+ vpminsw %xmm4,%xmm6,%xmm2
+ vpminub %xmm4,%xmm6,%xmm2
+ vpminud %xmm4,%xmm6,%xmm2
+ vpminuw %xmm4,%xmm6,%xmm2
+ vpmovmskb %xmm4,%ecx
+ vpmovsxbd %xmm4,%xmm6
+ vpmovsxbq %xmm4,%xmm6
+ vpmovsxbw %xmm4,%xmm6
+ vpmovsxdq %xmm4,%xmm6
+ vpmovsxwd %xmm4,%xmm6
+ vpmovsxwq %xmm4,%xmm6
+ vpmovzxbd %xmm4,%xmm6
+ vpmovzxbq %xmm4,%xmm6
+ vpmovzxbw %xmm4,%xmm6
+ vpmovzxdq %xmm4,%xmm6
+ vpmovzxwd %xmm4,%xmm6
+ vpmovzxwq %xmm4,%xmm6
+ vpmuldq %xmm4,%xmm6,%xmm2
+ vpmulhrsw %xmm4,%xmm6,%xmm2
+ vpmulhuw %xmm4,%xmm6,%xmm2
+ vpmulhw %xmm4,%xmm6,%xmm2
+ vpmulld %xmm4,%xmm6,%xmm2
+ vpmullw %xmm4,%xmm6,%xmm2
+ vpmuludq %xmm4,%xmm6,%xmm2
+ vpor %xmm4,%xmm6,%xmm2
+ vpsadbw %xmm4,%xmm6,%xmm2
+ vpshufb %xmm4,%xmm6,%xmm2
+ vpshufd $7,%xmm4,%xmm6
+ vpshufhw $7,%xmm4,%xmm6
+ vpshuflw $7,%xmm4,%xmm6
+ vpsignb %xmm4,%xmm6,%xmm2
+ vpsignd %xmm4,%xmm6,%xmm2
+ vpsignw %xmm4,%xmm6,%xmm2
+ vpslld %xmm4,%xmm6,%xmm2
+ vpslldq $7,%xmm4,%xmm6
+ vpsllq %xmm4,%xmm6,%xmm2
+ vpsllw %xmm4,%xmm6,%xmm2
+ vpsrad %xmm4,%xmm6,%xmm2
+ vpsraw %xmm4,%xmm6,%xmm2
+ vpsrld %xmm4,%xmm6,%xmm2
+ vpsrldq $7,%xmm4,%xmm6
+ vpsrlq %xmm4,%xmm6,%xmm2
+ vpsrlw %xmm4,%xmm6,%xmm2
+ vpsubb %xmm4,%xmm6,%xmm2
+ vpsubd %xmm4,%xmm6,%xmm2
+ vpsubq %xmm4,%xmm6,%xmm2
+ vpsubsb %xmm4,%xmm6,%xmm2
+ vpsubsw %xmm4,%xmm6,%xmm2
+ vpsubusb %xmm4,%xmm6,%xmm2
+ vpsubusw %xmm4,%xmm6,%xmm2
+ vpsubw %xmm4,%xmm6,%xmm2
+ vptest %ymm4,%ymm6
+ vpunpckhbw %xmm4,%xmm6,%xmm2
+ vpunpckhdq %xmm4,%xmm6,%xmm2
+ vpunpckhqdq %xmm4,%xmm6,%xmm2
+ vpunpckhwd %xmm4,%xmm6,%xmm2
+ vpunpcklbw %xmm4,%xmm6,%xmm2
+ vpunpckldq %xmm4,%xmm6,%xmm2
+ vpunpcklqdq %xmm4,%xmm6,%xmm2
+ vpunpcklwd %xmm4,%xmm6,%xmm2
+ vpxor %xmm4,%xmm6,%xmm2
+ vrcpps %ymm4,%ymm6
+ vrcpss %xmm4,%xmm6,%xmm2
+ vroundpd $7,%ymm6,%ymm2
+ vroundps $7,%ymm6,%ymm2
+ vroundsd $7,%xmm4,%xmm6,%xmm2
+ vroundss $7,%xmm4,%xmm6,%xmm2
+ vrsqrtps %ymm4,%ymm6
+ vrsqrtss %xmm4,%xmm6,%xmm2
+ vshufpd $7,%ymm4,%ymm6,%ymm2
+ vshufps $7,%ymm4,%ymm6,%ymm2
+ vsqrtpd %ymm4,%ymm6
+ vsqrtps %ymm4,%ymm6
+ vsqrtsd %xmm4,%xmm6,%xmm2
+ vsqrtss %xmm4,%xmm6,%xmm2
+ vstmxcsr (%ecx)
+ vsubpd %ymm4,%ymm6,%ymm2
+ vsubps %ymm4,%ymm6,%ymm2
+ vsubsd %xmm4,%xmm6,%xmm2
+ vsubss %xmm4,%xmm6,%xmm2
+ vucomisd %xmm4,%xmm6
+ vucomiss %xmm4,%xmm6
+ vunpckhpd %ymm4,%ymm6,%ymm2
+ vunpckhps %ymm4,%ymm6,%ymm2
+ vunpcklpd %ymm4,%ymm6,%ymm2
+ vunpcklps %ymm4,%ymm6,%ymm2
+ vxorpd %ymm4,%ymm6,%ymm2
+ vxorps %ymm4,%ymm6,%ymm2
+ vzeroall
+ vzeroupper
diff --git a/gas/testsuite/gas/i386/avx2-wig.d b/gas/testsuite/gas/i386/avx2-wig.d
new file mode 100644
index 0000000000..03ef21fcda
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx2-wig.d
@@ -0,0 +1,119 @@
+#as: -mvexwig=1
+#objdump: -dw
+#name: i386 AVX2 WIG insns with -mvexwig=1
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c4 e2 7d 2a 21 vmovntdqa \(%ecx\),%ymm4
+ +[a-f0-9]+: c4 e2 7d 2a 21 vmovntdqa \(%ecx\),%ymm4
+ +[a-f0-9]+: c4 e3 4d 42 d4 07 vmpsadbw \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 fd 1c f4 vpabsb %ymm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 1e f4 vpabsd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 1d f4 vpabsw %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 cd 6b d4 vpackssdw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 63 d4 vpacksswb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 2b d4 vpackusdw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 67 d4 vpackuswb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fc d4 vpaddb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fe d4 vpaddd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d4 d4 vpaddq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ec d4 vpaddsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ed d4 vpaddsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd dc d4 vpaddusb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd dd d4 vpaddusw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fd d4 vpaddw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 cd 0f d4 07 vpalignr \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd db d4 vpand %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd df d4 vpandn %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e0 d4 vpavgb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e3 d4 vpavgw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 cd 0e d4 07 vpblendw \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 74 d4 vpcmpeqb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 76 d4 vpcmpeqd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 29 d4 vpcmpeqq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 75 d4 vpcmpeqw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 64 d4 vpcmpgtb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 66 d4 vpcmpgtd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 37 d4 vpcmpgtq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 65 d4 vpcmpgtw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 02 d4 vphaddd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 03 d4 vphaddsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 01 d4 vphaddw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 4d 06 d4 vphsubd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 4d 07 d4 vphsubsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 4d 05 d4 vphsubw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 04 d4 vpmaddubsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f5 d4 vpmaddwd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3c d4 vpmaxsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3d d4 vpmaxsd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ee d4 vpmaxsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c5 cd de d4 vpmaxub %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3f d4 vpmaxud %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3e d4 vpmaxuw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 38 d4 vpminsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 39 d4 vpminsd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ea d4 vpminsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd da d4 vpminub %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3b d4 vpminud %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3a d4 vpminuw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fd d7 cc vpmovmskb %ymm4,%ecx
+ +[a-f0-9]+: c4 e2 fd 21 f4 vpmovsxbd %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 22 e4 vpmovsxbq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 20 e4 vpmovsxbw %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 25 e4 vpmovsxdq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 23 e4 vpmovsxwd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 24 f4 vpmovsxwq %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 31 f4 vpmovzxbd %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 32 e4 vpmovzxbq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 30 e4 vpmovzxbw %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 35 e4 vpmovzxdq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 33 e4 vpmovzxwd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 34 f4 vpmovzxwq %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 cd 28 d4 vpmuldq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 0b d4 vpmulhrsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e4 d4 vpmulhuw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e5 d4 vpmulhw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 40 d4 vpmulld %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d5 d4 vpmullw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f4 d4 vpmuludq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd eb d4 vpor %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f6 d4 vpsadbw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 00 d4 vpshufb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fd 70 d6 07 vpshufd \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fe 70 d6 07 vpshufhw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ff 70 d6 07 vpshuflw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 08 d4 vpsignb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 0a d4 vpsignd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 09 d4 vpsignw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 72 f6 07 vpslld \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 fe 07 vpslldq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 f6 07 vpsllq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 71 f6 07 vpsllw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 72 e6 07 vpsrad \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 71 e6 07 vpsraw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 72 d6 07 vpsrld \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 de 07 vpsrldq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 d6 07 vpsrlq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 71 d6 07 vpsrlw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f8 d4 vpsubb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fa d4 vpsubd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fb d4 vpsubq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e8 d4 vpsubsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e9 d4 vpsubsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d8 d4 vpsubusb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d9 d4 vpsubusw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f9 d4 vpsubw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 68 d4 vpunpckhbw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 6a d4 vpunpckhdq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 6d d4 vpunpckhqdq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 69 d4 vpunpckhwd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 60 d4 vpunpcklbw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 62 d4 vpunpckldq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 6c d4 vpunpcklqdq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 61 d4 vpunpcklwd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ef d4 vpxor %ymm4,%ymm6,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx2-wig.s b/gas/testsuite/gas/i386/avx2-wig.s
new file mode 100644
index 0000000000..6ebc5e7848
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx2-wig.s
@@ -0,0 +1,113 @@
+# Check AVX2 WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vmovntdqa (%ecx),%ymm4
+ vmovntdqa (%ecx),%ymm4
+ vmpsadbw $7,%ymm4,%ymm6,%ymm2
+ vpabsb %ymm4,%ymm6
+ vpabsd %ymm4,%ymm6
+ vpabsw %ymm4,%ymm6
+ vpackssdw %ymm4,%ymm6,%ymm2
+ vpacksswb %ymm4,%ymm6,%ymm2
+ vpackusdw %ymm4,%ymm6,%ymm2
+ vpackuswb %ymm4,%ymm6,%ymm2
+ vpaddb %ymm4,%ymm6,%ymm2
+ vpaddd %ymm4,%ymm6,%ymm2
+ vpaddq %ymm4,%ymm6,%ymm2
+ vpaddsb %ymm4,%ymm6,%ymm2
+ vpaddsw %ymm4,%ymm6,%ymm2
+ vpaddusb %ymm4,%ymm6,%ymm2
+ vpaddusw %ymm4,%ymm6,%ymm2
+ vpaddw %ymm4,%ymm6,%ymm2
+ vpalignr $7,%ymm4,%ymm6,%ymm2
+ vpand %ymm4,%ymm6,%ymm2
+ vpandn %ymm4,%ymm6,%ymm2
+ vpavgb %ymm4,%ymm6,%ymm2
+ vpavgw %ymm4,%ymm6,%ymm2
+ vpblendw $7,%ymm4,%ymm6,%ymm2
+ vpcmpeqb %ymm4,%ymm6,%ymm2
+ vpcmpeqd %ymm4,%ymm6,%ymm2
+ vpcmpeqq %ymm4,%ymm6,%ymm2
+ vpcmpeqw %ymm4,%ymm6,%ymm2
+ vpcmpgtb %ymm4,%ymm6,%ymm2
+ vpcmpgtd %ymm4,%ymm6,%ymm2
+ vpcmpgtq %ymm4,%ymm6,%ymm2
+ vpcmpgtw %ymm4,%ymm6,%ymm2
+ vphaddd %ymm4,%ymm6,%ymm2
+ vphaddsw %ymm4,%ymm6,%ymm2
+ vphaddw %ymm4,%ymm6,%ymm2
+ vphsubd %ymm4,%ymm6,%ymm2
+ vphsubsw %ymm4,%ymm6,%ymm2
+ vphsubw %ymm4,%ymm6,%ymm2
+ vpmaddubsw %ymm4,%ymm6,%ymm2
+ vpmaddwd %ymm4,%ymm6,%ymm2
+ vpmaxsb %ymm4,%ymm6,%ymm2
+ vpmaxsd %ymm4,%ymm6,%ymm2
+ vpmaxsw %ymm4,%ymm6,%ymm2
+ vpmaxub %ymm4,%ymm6,%ymm2
+ vpmaxud %ymm4,%ymm6,%ymm2
+ vpmaxuw %ymm4,%ymm6,%ymm2
+ vpminsb %ymm4,%ymm6,%ymm2
+ vpminsd %ymm4,%ymm6,%ymm2
+ vpminsw %ymm4,%ymm6,%ymm2
+ vpminub %ymm4,%ymm6,%ymm2
+ vpminud %ymm4,%ymm6,%ymm2
+ vpminuw %ymm4,%ymm6,%ymm2
+ vpmovmskb %ymm4,%ecx
+ vpmovsxbd %xmm4,%ymm6
+ vpmovsxbq %xmm4,%ymm4
+ vpmovsxbw %xmm4,%ymm4
+ vpmovsxdq %xmm4,%ymm4
+ vpmovsxwd %xmm4,%ymm4
+ vpmovsxwq %xmm4,%ymm6
+ vpmovzxbd %xmm4,%ymm6
+ vpmovzxbq %xmm4,%ymm4
+ vpmovzxbw %xmm4,%ymm4
+ vpmovzxdq %xmm4,%ymm4
+ vpmovzxwd %xmm4,%ymm4
+ vpmovzxwq %xmm4,%ymm6
+ vpmuldq %ymm4,%ymm6,%ymm2
+ vpmulhrsw %ymm4,%ymm6,%ymm2
+ vpmulhuw %ymm4,%ymm6,%ymm2
+ vpmulhw %ymm4,%ymm6,%ymm2
+ vpmulld %ymm4,%ymm6,%ymm2
+ vpmullw %ymm4,%ymm6,%ymm2
+ vpmuludq %ymm4,%ymm6,%ymm2
+ vpor %ymm4,%ymm6,%ymm2
+ vpsadbw %ymm4,%ymm6,%ymm2
+ vpshufb %ymm4,%ymm6,%ymm2
+ vpshufd $7,%ymm6,%ymm2
+ vpshufhw $7,%ymm6,%ymm2
+ vpshuflw $7,%ymm6,%ymm2
+ vpsignb %ymm4,%ymm6,%ymm2
+ vpsignd %ymm4,%ymm6,%ymm2
+ vpsignw %ymm4,%ymm6,%ymm2
+ vpslld $7,%ymm6,%ymm2
+ vpslldq $7,%ymm6,%ymm2
+ vpsllq $7,%ymm6,%ymm2
+ vpsllw $7,%ymm6,%ymm2
+ vpsrad $7,%ymm6,%ymm2
+ vpsraw $7,%ymm6,%ymm2
+ vpsrld $7,%ymm6,%ymm2
+ vpsrldq $7,%ymm6,%ymm2
+ vpsrlq $7,%ymm6,%ymm2
+ vpsrlw $7,%ymm6,%ymm2
+ vpsubb %ymm4,%ymm6,%ymm2
+ vpsubd %ymm4,%ymm6,%ymm2
+ vpsubq %ymm4,%ymm6,%ymm2
+ vpsubsb %ymm4,%ymm6,%ymm2
+ vpsubsw %ymm4,%ymm6,%ymm2
+ vpsubusb %ymm4,%ymm6,%ymm2
+ vpsubusw %ymm4,%ymm6,%ymm2
+ vpsubw %ymm4,%ymm6,%ymm2
+ vpunpckhbw %ymm4,%ymm6,%ymm2
+ vpunpckhdq %ymm4,%ymm6,%ymm2
+ vpunpckhqdq %ymm4,%ymm6,%ymm2
+ vpunpckhwd %ymm4,%ymm6,%ymm2
+ vpunpcklbw %ymm4,%ymm6,%ymm2
+ vpunpckldq %ymm4,%ymm6,%ymm2
+ vpunpcklqdq %ymm4,%ymm6,%ymm2
+ vpunpcklwd %ymm4,%ymm6,%ymm2
+ vpxor %ymm4,%ymm6,%ymm2
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index bd7acd1ed9..90da612f5f 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -213,6 +213,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx2-intel"
run_dump_test "avx-gather"
run_dump_test "avx-gather-intel"
+ run_dump_test "avx-wig"
+ run_dump_test "avx2-wig"
run_dump_test "avx512f"
run_dump_test "avx512f-intel"
run_dump_test "avx512f-opts"
@@ -732,6 +734,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-avx2-intel"
run_dump_test "x86-64-avx-gather"
run_dump_test "x86-64-avx-gather-intel"
+ run_dump_test "x86-64-avx-wig"
+ run_dump_test "x86-64-avx2-wig"
run_dump_test "x86-64-avx512f"
run_dump_test "x86-64-avx512f-intel"
run_dump_test "x86-64-avx512f-opts"
diff --git a/gas/testsuite/gas/i386/x86-64-avx-wig.d b/gas/testsuite/gas/i386/x86-64-avx-wig.d
new file mode 100644
index 0000000000..90d61be4f5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-wig.d
@@ -0,0 +1,256 @@
+#as: -mvexwig=1
+#objdump: -dw
+#name: x86-64 AVX WIG insns with -mvexwig=1
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c4 e1 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd d0 d4 vaddsubpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cf d0 d4 vaddsubps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 c9 de d4 vaesdec %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 df d4 vaesdeclast %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 dc d4 vaesenc %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 dd d4 vaesenclast %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 f9 db f4 vaesimc %xmm4,%xmm6
+ +[a-f0-9]+: c4 e3 f9 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e3 cd 0d d4 07 vblendpd \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 cd 0c d4 07 vblendps \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 2f f4 vcomisd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 2f f4 vcomiss %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fe e6 e4 vcvtdq2pd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e1 fc 5b f4 vcvtdq2ps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fb e6 f4 vcvtpd2dq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 f9 5a f4 vcvtpd2ps %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fd 5b f4 vcvtps2dq %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 5a e4 vcvtps2pd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e1 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
+ +[a-f0-9]+: c4 e1 fe 5b f4 vcvttps2dq %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 cd 5e d4 vdivpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5e d4 vdivps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5e d4 vdivsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5e d4 vdivss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 cd 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 f9 17 e1 07 vextractps \$0x7,%xmm4,%rcx
+ +[a-f0-9]+: c4 e1 cd 7c d4 vhaddpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cf 7c d4 vhaddps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 7d d4 vhsubpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cf 7d d4 vhsubps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 c9 21 d4 07 vinsertps \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ff f0 21 vlddqu \(%rcx\),%ymm4
+ +[a-f0-9]+: c4 e1 f8 ae 11 vldmxcsr \(%rcx\)
+ +[a-f0-9]+: c4 e1 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 cd 5f d4 vmaxpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5f d4 vmaxps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5f d4 vmaxsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5f d4 vmaxss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd 5d d4 vminpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5d d4 vminps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5d d4 vminsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5d d4 vminss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fd 28 f4 vmovapd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 28 f4 vmovaps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 29 e6 vmovapd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 29 e6 vmovaps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ff 12 f4 vmovddup %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 6f f4 vmovdqa %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fe 6f f4 vmovdqu %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 7f e6 vmovdqa %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fe 7f e6 vmovdqu %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 c8 12 d4 vmovhlps %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 d9 16 31 vmovhpd \(%rcx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f9 17 21 vmovhpd %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 d8 16 31 vmovhps \(%rcx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 17 21 vmovhps %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 d9 12 31 vmovlpd \(%rcx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f9 13 21 vmovlpd %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 d8 12 31 vmovlps \(%rcx\),%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 13 21 vmovlps %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 f9 50 cc vmovmskpd %xmm4,%rcx
+ +[a-f0-9]+: c4 e1 f8 50 cc vmovmskps %xmm4,%rcx
+ +[a-f0-9]+: c4 e1 fd e7 21 vmovntdq %ymm4,\(%rcx\)
+ +[a-f0-9]+: c4 e2 f9 2a 21 vmovntdqa \(%rcx\),%xmm4
+ +[a-f0-9]+: c4 e1 fd 2b 21 vmovntpd %ymm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 fc 2b 21 vmovntps %ymm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 fa 7e f4 vmovq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f9 d6 21 vmovq %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx
+ +[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4
+ +[a-f0-9]+: c4 e1 fb 10 21 vmovsd \(%rcx\),%xmm4
+ +[a-f0-9]+: c4 e1 fb 11 21 vmovsd %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 fe 16 f4 vmovshdup %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fe 12 f4 vmovsldup %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fa 10 21 vmovss \(%rcx\),%xmm4
+ +[a-f0-9]+: c4 e1 fa 11 21 vmovss %xmm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 fd 10 f4 vmovupd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fd 11 21 vmovupd %ymm4,\(%rcx\)
+ +[a-f0-9]+: c4 e1 fc 10 f4 vmovups %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 11 21 vmovups %ymm4,\(%rcx\)
+ +[a-f0-9]+: c4 e3 c9 42 d4 07 vmpsadbw \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd 59 d4 vmulpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 59 d4 vmulps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 59 d4 vmulsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 59 d4 vmulss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 f9 1c f4 vpabsb %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 1e f4 vpabsd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 1d f4 vpabsw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 c9 6b d4 vpackssdw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 63 d4 vpacksswb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 2b d4 vpackusdw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 67 d4 vpackuswb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fc d4 vpaddb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fe d4 vpaddd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d4 d4 vpaddq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ec d4 vpaddsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ed d4 vpaddsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 dc d4 vpaddusb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 dd d4 vpaddusw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fd d4 vpaddw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 0f d4 07 vpalignr \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 db d4 vpand %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 df d4 vpandn %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e0 d4 vpavgb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e3 d4 vpavgw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 0e d4 07 vpblendw \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 11 vpclmulhqhqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 01 vpclmulhqlqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 10 vpclmullqhqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 00 vpclmullqlqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 44 d4 07 vpclmulqdq \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 74 d4 vpcmpeqb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 76 d4 vpcmpeqd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 29 d4 vpcmpeqq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 75 d4 vpcmpeqw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 64 d4 vpcmpgtb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 66 d4 vpcmpgtd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 37 d4 vpcmpgtq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 f9 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e3 f9 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 02 d4 vphaddd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 03 d4 vphaddsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 01 d4 vphaddw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 f9 41 f4 vphminposuw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 06 d4 vphsubd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 07 d4 vphsubsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 05 d4 vphsubw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3d d4 vpmaxsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ee d4 vpmaxsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c5 c9 de d4 vpmaxub %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3f d4 vpmaxud %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3e d4 vpmaxuw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 38 d4 vpminsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 39 d4 vpminsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ea d4 vpminsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 da d4 vpminub %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3b d4 vpminud %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 3a d4 vpminuw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 d7 cc vpmovmskb %xmm4,%rcx
+ +[a-f0-9]+: c4 e2 f9 21 f4 vpmovsxbd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 22 f4 vpmovsxbq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 20 f4 vpmovsxbw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 25 f4 vpmovsxdq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 23 f4 vpmovsxwd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 24 f4 vpmovsxwq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 31 f4 vpmovzxbd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 32 f4 vpmovzxbq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 30 f4 vpmovzxbw %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 35 f4 vpmovzxdq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 33 f4 vpmovzxwd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 f9 34 f4 vpmovzxwq %xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 28 d4 vpmuldq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 0b d4 vpmulhrsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e4 d4 vpmulhuw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e5 d4 vpmulhw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 40 d4 vpmulld %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d5 d4 vpmullw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f4 d4 vpmuludq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 eb d4 vpor %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f6 d4 vpsadbw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 00 d4 vpshufb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 70 f4 07 vpshufd \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fa 70 f4 07 vpshufhw \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 fb 70 f4 07 vpshuflw \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e2 c9 08 d4 vpsignb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 0a d4 vpsignd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 c9 09 d4 vpsignw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f2 d4 vpslld %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 73 fc 07 vpslldq \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 c9 f3 d4 vpsllq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f1 d4 vpsllw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e2 d4 vpsrad %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e1 d4 vpsraw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d2 d4 vpsrld %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 73 dc 07 vpsrldq \$0x7,%xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 c9 d3 d4 vpsrlq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d1 d4 vpsrlw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f8 d4 vpsubb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fa d4 vpsubd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 fb d4 vpsubq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e8 d4 vpsubsb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 e9 d4 vpsubsw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d8 d4 vpsubusb %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 d9 d4 vpsubusw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 f9 d4 vpsubw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e2 fd 17 f4 vptest %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 c9 68 d4 vpunpckhbw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 6a d4 vpunpckhdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 6d d4 vpunpckhqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 69 d4 vpunpckhwd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 60 d4 vpunpcklbw %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 62 d4 vpunpckldq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 6c d4 vpunpcklqdq %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 61 d4 vpunpcklwd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 c9 ef d4 vpxor %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fc 53 f4 vrcpps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ca 53 d4 vrcpss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 fd 09 d6 07 vroundpd \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 fd 08 d6 07 vroundps \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 c9 0b d4 07 vroundsd \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e3 c9 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 fc 52 f4 vrsqrtps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 ca 52 d4 vrsqrtss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 cd c6 d4 07 vshufpd \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fd 51 f4 vsqrtpd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 fc 51 f4 vsqrtps %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 cb 51 d4 vsqrtsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 51 d4 vsqrtss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f8 ae 19 vstmxcsr \(%rcx\)
+ +[a-f0-9]+: c4 e1 cd 5c d4 vsubpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 5c d4 vsubps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cb 5c d4 vsubsd %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 ca 5c d4 vsubss %xmm4,%xmm6,%xmm2
+ +[a-f0-9]+: c4 e1 f9 2e f4 vucomisd %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 f8 2e f4 vucomiss %xmm4,%xmm6
+ +[a-f0-9]+: c4 e1 cd 15 d4 vunpckhpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 15 d4 vunpckhps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 14 d4 vunpcklpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 14 d4 vunpcklps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 57 d4 vxorpd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cc 57 d4 vxorps %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fc 77 vzeroall
+ +[a-f0-9]+: c4 e1 f8 77 vzeroupper
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-wig.s b/gas/testsuite/gas/i386/x86-64-avx-wig.s
new file mode 100644
index 0000000000..74ef15251c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-wig.s
@@ -0,0 +1,250 @@
+# Check AVX WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vaddpd %ymm4,%ymm6,%ymm2
+ vaddps %ymm4,%ymm6,%ymm2
+ vaddsd %xmm4,%xmm6,%xmm2
+ vaddss %xmm4,%xmm6,%xmm2
+ vaddsubpd %ymm4,%ymm6,%ymm2
+ vaddsubps %ymm4,%ymm6,%ymm2
+ vaesdec %xmm4,%xmm6,%xmm2
+ vaesdeclast %xmm4,%xmm6,%xmm2
+ vaesenc %xmm4,%xmm6,%xmm2
+ vaesenclast %xmm4,%xmm6,%xmm2
+ vaesimc %xmm4,%xmm6
+ vaeskeygenassist $7,%xmm4,%xmm6
+ vblendpd $7,%ymm4,%ymm6,%ymm2
+ vblendps $7,%ymm4,%ymm6,%ymm2
+ vcmppd $7,%ymm4,%ymm6,%ymm2
+ vcmpps $7,%ymm4,%ymm6,%ymm2
+ vcmpsd $7,%xmm4,%xmm6,%xmm2
+ vcmpss $7,%xmm4,%xmm6,%xmm2
+ vcomisd %xmm4,%xmm6
+ vcomiss %xmm4,%xmm6
+ vcvtdq2pd %xmm4,%ymm4
+ vcvtdq2ps %ymm4,%ymm6
+ vcvtpd2dqy %ymm4,%xmm4
+ vcvtpd2dqx %xmm4,%xmm6
+ vcvtpd2dqy %ymm4,%xmm4
+ vcvtpd2psy %ymm4,%xmm4
+ vcvtpd2psx %xmm4,%xmm6
+ vcvtpd2psy %ymm4,%xmm4
+ vcvtps2dq %ymm4,%ymm6
+ vcvtps2pd %xmm4,%ymm4
+ vcvtsd2ss %xmm4,%xmm6,%xmm2
+ vcvttpd2dqy %ymm4,%xmm4
+ vcvttpd2dqx %xmm4,%xmm6
+ vcvttpd2dqy %ymm4,%xmm4
+ vcvttps2dq %ymm4,%ymm6
+ vdivpd %ymm4,%ymm6,%ymm2
+ vdivps %ymm4,%ymm6,%ymm2
+ vdivsd %xmm4,%xmm6,%xmm2
+ vdivss %xmm4,%xmm6,%xmm2
+ vdppd $7,%xmm4,%xmm6,%xmm2
+ vdpps $7,%ymm4,%ymm6,%ymm2
+ vextractps $7,%xmm4,%rcx
+ vhaddpd %ymm4,%ymm6,%ymm2
+ vhaddps %ymm4,%ymm6,%ymm2
+ vhsubpd %ymm4,%ymm6,%ymm2
+ vhsubps %ymm4,%ymm6,%ymm2
+ vinsertps $7,%xmm4,%xmm6,%xmm2
+ vlddqu (%rcx),%ymm4
+ vldmxcsr (%rcx)
+ vmaskmovdqu %xmm4,%xmm6
+ vmaxpd %ymm4,%ymm6,%ymm2
+ vmaxps %ymm4,%ymm6,%ymm2
+ vmaxsd %xmm4,%xmm6,%xmm2
+ vmaxss %xmm4,%xmm6,%xmm2
+ vminpd %ymm4,%ymm6,%ymm2
+ vminps %ymm4,%ymm6,%ymm2
+ vminsd %xmm4,%xmm6,%xmm2
+ vminss %xmm4,%xmm6,%xmm2
+ vmovapd %ymm4,%ymm6
+ vmovaps %ymm4,%ymm6
+ {store} vmovapd %ymm4,%ymm6
+ {store} vmovaps %ymm4,%ymm6
+ vmovddup %ymm4,%ymm6
+ vmovdqa %ymm4,%ymm6
+ vmovdqu %ymm4,%ymm6
+ {store} vmovdqa %ymm4,%ymm6
+ {store} vmovdqu %ymm4,%ymm6
+ vmovhlps %xmm4,%xmm6,%xmm2
+ vmovhpd (%rcx),%xmm4,%xmm6
+ vmovhpd %xmm4,(%rcx)
+ vmovhps (%rcx),%xmm4,%xmm6
+ vmovhps %xmm4,(%rcx)
+ vmovlhps %xmm4,%xmm6,%xmm2
+ vmovlpd (%rcx),%xmm4,%xmm6
+ vmovlpd %xmm4,(%rcx)
+ vmovlps (%rcx),%xmm4,%xmm6
+ vmovlps %xmm4,(%rcx)
+ vmovmskpd %xmm4,%rcx
+ vmovmskps %xmm4,%rcx
+ vmovntdq %ymm4,(%rcx)
+ vmovntdqa (%rcx),%xmm4
+ vmovntpd %ymm4,(%rcx)
+ vmovntps %ymm4,(%rcx)
+ vmovq %xmm4,%xmm6
+ vmovq %xmm4,(%rcx)
+ vmovq %xmm4,%rcx
+ vmovq %rcx,%xmm4
+ vmovsd (%rcx),%xmm4
+ vmovsd %xmm4,(%rcx)
+ vmovshdup %ymm4,%ymm6
+ vmovsldup %ymm4,%ymm6
+ vmovss (%rcx),%xmm4
+ vmovss %xmm4,(%rcx)
+ vmovupd %ymm4,%ymm6
+ vmovupd %ymm4,(%rcx)
+ vmovups %ymm4,%ymm6
+ vmovups %ymm4,(%rcx)
+ vmpsadbw $7,%xmm4,%xmm6,%xmm2
+ vmulpd %ymm4,%ymm6,%ymm2
+ vmulps %ymm4,%ymm6,%ymm2
+ vmulsd %xmm4,%xmm6,%xmm2
+ vmulss %xmm4,%xmm6,%xmm2
+ vpabsb %xmm4,%xmm6
+ vpabsd %xmm4,%xmm6
+ vpabsw %xmm4,%xmm6
+ vpackssdw %xmm4,%xmm6,%xmm2
+ vpacksswb %xmm4,%xmm6,%xmm2
+ vpackusdw %xmm4,%xmm6,%xmm2
+ vpackuswb %xmm4,%xmm6,%xmm2
+ vpaddb %xmm4,%xmm6,%xmm2
+ vpaddd %xmm4,%xmm6,%xmm2
+ vpaddq %xmm4,%xmm6,%xmm2
+ vpaddsb %xmm4,%xmm6,%xmm2
+ vpaddsw %xmm4,%xmm6,%xmm2
+ vpaddusb %xmm4,%xmm6,%xmm2
+ vpaddusw %xmm4,%xmm6,%xmm2
+ vpaddw %xmm4,%xmm6,%xmm2
+ vpalignr $7,%xmm4,%xmm6,%xmm2
+ vpand %xmm4,%xmm6,%xmm2
+ vpandn %xmm4,%xmm6,%xmm2
+ vpavgb %xmm4,%xmm6,%xmm2
+ vpavgw %xmm4,%xmm6,%xmm2
+ vpblendw $7,%xmm4,%xmm6,%xmm2
+ vpclmulhqhqdq %xmm4,%xmm6,%xmm2
+ vpclmulhqlqdq %xmm4,%xmm6,%xmm2
+ vpclmullqhqdq %xmm4,%xmm6,%xmm2
+ vpclmullqlqdq %xmm4,%xmm6,%xmm2
+ vpclmulqdq $7,%xmm4,%xmm6,%xmm2
+ vpcmpeqb %xmm4,%xmm6,%xmm2
+ vpcmpeqd %xmm4,%xmm6,%xmm2
+ vpcmpeqq %xmm4,%xmm6,%xmm2
+ vpcmpeqw %xmm4,%xmm6,%xmm2
+ vpcmpgtb %xmm4,%xmm6,%xmm2
+ vpcmpgtd %xmm4,%xmm6,%xmm2
+ vpcmpgtq %xmm4,%xmm6,%xmm2
+ vpcmpgtw %xmm4,%xmm6,%xmm2
+ vpcmpistri $7,%xmm4,%xmm6
+ vpcmpistrm $7,%xmm4,%xmm6
+ vphaddd %xmm4,%xmm6,%xmm2
+ vphaddsw %xmm4,%xmm6,%xmm2
+ vphaddw %xmm4,%xmm6,%xmm2
+ vphminposuw %xmm4,%xmm6
+ vphsubd %xmm4,%xmm6,%xmm2
+ vphsubsw %xmm4,%xmm6,%xmm2
+ vphsubw %xmm4,%xmm6,%xmm2
+ vpmaddubsw %xmm4,%xmm6,%xmm2
+ vpmaddwd %xmm4,%xmm6,%xmm2
+ vpmaxsb %xmm4,%xmm6,%xmm2
+ vpmaxsd %xmm4,%xmm6,%xmm2
+ vpmaxsw %xmm4,%xmm6,%xmm2
+ vpmaxub %xmm4,%xmm6,%xmm2
+ vpmaxud %xmm4,%xmm6,%xmm2
+ vpmaxuw %xmm4,%xmm6,%xmm2
+ vpminsb %xmm4,%xmm6,%xmm2
+ vpminsd %xmm4,%xmm6,%xmm2
+ vpminsw %xmm4,%xmm6,%xmm2
+ vpminub %xmm4,%xmm6,%xmm2
+ vpminud %xmm4,%xmm6,%xmm2
+ vpminuw %xmm4,%xmm6,%xmm2
+ vpmovmskb %xmm4,%rcx
+ vpmovsxbd %xmm4,%xmm6
+ vpmovsxbq %xmm4,%xmm6
+ vpmovsxbw %xmm4,%xmm6
+ vpmovsxdq %xmm4,%xmm6
+ vpmovsxwd %xmm4,%xmm6
+ vpmovsxwq %xmm4,%xmm6
+ vpmovzxbd %xmm4,%xmm6
+ vpmovzxbq %xmm4,%xmm6
+ vpmovzxbw %xmm4,%xmm6
+ vpmovzxdq %xmm4,%xmm6
+ vpmovzxwd %xmm4,%xmm6
+ vpmovzxwq %xmm4,%xmm6
+ vpmuldq %xmm4,%xmm6,%xmm2
+ vpmulhrsw %xmm4,%xmm6,%xmm2
+ vpmulhuw %xmm4,%xmm6,%xmm2
+ vpmulhw %xmm4,%xmm6,%xmm2
+ vpmulld %xmm4,%xmm6,%xmm2
+ vpmullw %xmm4,%xmm6,%xmm2
+ vpmuludq %xmm4,%xmm6,%xmm2
+ vpor %xmm4,%xmm6,%xmm2
+ vpsadbw %xmm4,%xmm6,%xmm2
+ vpshufb %xmm4,%xmm6,%xmm2
+ vpshufd $7,%xmm4,%xmm6
+ vpshufhw $7,%xmm4,%xmm6
+ vpshuflw $7,%xmm4,%xmm6
+ vpsignb %xmm4,%xmm6,%xmm2
+ vpsignd %xmm4,%xmm6,%xmm2
+ vpsignw %xmm4,%xmm6,%xmm2
+ vpslld %xmm4,%xmm6,%xmm2
+ vpslldq $7,%xmm4,%xmm6
+ vpsllq %xmm4,%xmm6,%xmm2
+ vpsllw %xmm4,%xmm6,%xmm2
+ vpsrad %xmm4,%xmm6,%xmm2
+ vpsraw %xmm4,%xmm6,%xmm2
+ vpsrld %xmm4,%xmm6,%xmm2
+ vpsrldq $7,%xmm4,%xmm6
+ vpsrlq %xmm4,%xmm6,%xmm2
+ vpsrlw %xmm4,%xmm6,%xmm2
+ vpsubb %xmm4,%xmm6,%xmm2
+ vpsubd %xmm4,%xmm6,%xmm2
+ vpsubq %xmm4,%xmm6,%xmm2
+ vpsubsb %xmm4,%xmm6,%xmm2
+ vpsubsw %xmm4,%xmm6,%xmm2
+ vpsubusb %xmm4,%xmm6,%xmm2
+ vpsubusw %xmm4,%xmm6,%xmm2
+ vpsubw %xmm4,%xmm6,%xmm2
+ vptest %ymm4,%ymm6
+ vpunpckhbw %xmm4,%xmm6,%xmm2
+ vpunpckhdq %xmm4,%xmm6,%xmm2
+ vpunpckhqdq %xmm4,%xmm6,%xmm2
+ vpunpckhwd %xmm4,%xmm6,%xmm2
+ vpunpcklbw %xmm4,%xmm6,%xmm2
+ vpunpckldq %xmm4,%xmm6,%xmm2
+ vpunpcklqdq %xmm4,%xmm6,%xmm2
+ vpunpcklwd %xmm4,%xmm6,%xmm2
+ vpxor %xmm4,%xmm6,%xmm2
+ vrcpps %ymm4,%ymm6
+ vrcpss %xmm4,%xmm6,%xmm2
+ vroundpd $7,%ymm6,%ymm2
+ vroundps $7,%ymm6,%ymm2
+ vroundsd $7,%xmm4,%xmm6,%xmm2
+ vroundss $7,%xmm4,%xmm6,%xmm2
+ vrsqrtps %ymm4,%ymm6
+ vrsqrtss %xmm4,%xmm6,%xmm2
+ vshufpd $7,%ymm4,%ymm6,%ymm2
+ vshufps $7,%ymm4,%ymm6,%ymm2
+ vsqrtpd %ymm4,%ymm6
+ vsqrtps %ymm4,%ymm6
+ vsqrtsd %xmm4,%xmm6,%xmm2
+ vsqrtss %xmm4,%xmm6,%xmm2
+ vstmxcsr (%rcx)
+ vsubpd %ymm4,%ymm6,%ymm2
+ vsubps %ymm4,%ymm6,%ymm2
+ vsubsd %xmm4,%xmm6,%xmm2
+ vsubss %xmm4,%xmm6,%xmm2
+ vucomisd %xmm4,%xmm6
+ vucomiss %xmm4,%xmm6
+ vunpckhpd %ymm4,%ymm6,%ymm2
+ vunpckhps %ymm4,%ymm6,%ymm2
+ vunpcklpd %ymm4,%ymm6,%ymm2
+ vunpcklps %ymm4,%ymm6,%ymm2
+ vxorpd %ymm4,%ymm6,%ymm2
+ vxorps %ymm4,%ymm6,%ymm2
+ vzeroall
+ vzeroupper
diff --git a/gas/testsuite/gas/i386/x86-64-avx2-wig.d b/gas/testsuite/gas/i386/x86-64-avx2-wig.d
new file mode 100644
index 0000000000..55f85d6d62
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx2-wig.d
@@ -0,0 +1,119 @@
+#as: -mvexwig=1
+#objdump: -dw
+#name: x86-64 AVX2 WIG insns with -mvexwig=1
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c4 e2 7d 2a 21 vmovntdqa \(%rcx\),%ymm4
+ +[a-f0-9]+: c4 e2 7d 2a 21 vmovntdqa \(%rcx\),%ymm4
+ +[a-f0-9]+: c4 e3 4d 42 d4 07 vmpsadbw \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 fd 1c f4 vpabsb %ymm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 1e f4 vpabsd %ymm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 1d f4 vpabsw %ymm4,%ymm6
+ +[a-f0-9]+: c4 e1 cd 6b d4 vpackssdw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 63 d4 vpacksswb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 2b d4 vpackusdw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 67 d4 vpackuswb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fc d4 vpaddb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fe d4 vpaddd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d4 d4 vpaddq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ec d4 vpaddsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ed d4 vpaddsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd dc d4 vpaddusb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd dd d4 vpaddusw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fd d4 vpaddw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 cd 0f d4 07 vpalignr \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd db d4 vpand %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd df d4 vpandn %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e0 d4 vpavgb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e3 d4 vpavgw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e3 cd 0e d4 07 vpblendw \$0x7,%ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 74 d4 vpcmpeqb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 76 d4 vpcmpeqd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 29 d4 vpcmpeqq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 75 d4 vpcmpeqw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 64 d4 vpcmpgtb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 66 d4 vpcmpgtd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 37 d4 vpcmpgtq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 65 d4 vpcmpgtw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 02 d4 vphaddd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 03 d4 vphaddsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 01 d4 vphaddw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 4d 06 d4 vphsubd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 4d 07 d4 vphsubsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 4d 05 d4 vphsubw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 04 d4 vpmaddubsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f5 d4 vpmaddwd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3c d4 vpmaxsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3d d4 vpmaxsd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ee d4 vpmaxsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c5 cd de d4 vpmaxub %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3f d4 vpmaxud %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3e d4 vpmaxuw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 38 d4 vpminsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 39 d4 vpminsd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ea d4 vpminsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd da d4 vpminub %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3b d4 vpminud %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 3a d4 vpminuw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fd d7 cc vpmovmskb %ymm4,%rcx
+ +[a-f0-9]+: c4 e2 fd 21 f4 vpmovsxbd %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 22 e4 vpmovsxbq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 20 e4 vpmovsxbw %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 25 e4 vpmovsxdq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 23 e4 vpmovsxwd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 24 f4 vpmovsxwq %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 31 f4 vpmovzxbd %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 fd 32 e4 vpmovzxbq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 30 e4 vpmovzxbw %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 35 e4 vpmovzxdq %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 33 e4 vpmovzxwd %xmm4,%ymm4
+ +[a-f0-9]+: c4 e2 fd 34 f4 vpmovzxwq %xmm4,%ymm6
+ +[a-f0-9]+: c4 e2 cd 28 d4 vpmuldq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 0b d4 vpmulhrsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e4 d4 vpmulhuw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e5 d4 vpmulhw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 40 d4 vpmulld %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d5 d4 vpmullw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f4 d4 vpmuludq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd eb d4 vpor %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f6 d4 vpsadbw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 00 d4 vpshufb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fd 70 d6 07 vpshufd \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 fe 70 d6 07 vpshufhw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ff 70 d6 07 vpshuflw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 08 d4 vpsignb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 0a d4 vpsignd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e2 cd 09 d4 vpsignw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 72 f6 07 vpslld \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 fe 07 vpslldq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 f6 07 vpsllq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 71 f6 07 vpsllw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 72 e6 07 vpsrad \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 71 e6 07 vpsraw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 72 d6 07 vpsrld \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 de 07 vpsrldq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 73 d6 07 vpsrlq \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 ed 71 d6 07 vpsrlw \$0x7,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f8 d4 vpsubb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fa d4 vpsubd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd fb d4 vpsubq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e8 d4 vpsubsb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd e9 d4 vpsubsw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d8 d4 vpsubusb %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd d9 d4 vpsubusw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd f9 d4 vpsubw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 68 d4 vpunpckhbw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 6a d4 vpunpckhdq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 6d d4 vpunpckhqdq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 69 d4 vpunpckhwd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 60 d4 vpunpcklbw %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 62 d4 vpunpckldq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 6c d4 vpunpcklqdq %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd 61 d4 vpunpcklwd %ymm4,%ymm6,%ymm2
+ +[a-f0-9]+: c4 e1 cd ef d4 vpxor %ymm4,%ymm6,%ymm2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx2-wig.s b/gas/testsuite/gas/i386/x86-64-avx2-wig.s
new file mode 100644
index 0000000000..162a9f84bb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx2-wig.s
@@ -0,0 +1,113 @@
+# Check AVX2 WIG instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vmovntdqa (%rcx),%ymm4
+ vmovntdqa (%rcx),%ymm4
+ vmpsadbw $7,%ymm4,%ymm6,%ymm2
+ vpabsb %ymm4,%ymm6
+ vpabsd %ymm4,%ymm6
+ vpabsw %ymm4,%ymm6
+ vpackssdw %ymm4,%ymm6,%ymm2
+ vpacksswb %ymm4,%ymm6,%ymm2
+ vpackusdw %ymm4,%ymm6,%ymm2
+ vpackuswb %ymm4,%ymm6,%ymm2
+ vpaddb %ymm4,%ymm6,%ymm2
+ vpaddd %ymm4,%ymm6,%ymm2
+ vpaddq %ymm4,%ymm6,%ymm2
+ vpaddsb %ymm4,%ymm6,%ymm2
+ vpaddsw %ymm4,%ymm6,%ymm2
+ vpaddusb %ymm4,%ymm6,%ymm2
+ vpaddusw %ymm4,%ymm6,%ymm2
+ vpaddw %ymm4,%ymm6,%ymm2
+ vpalignr $7,%ymm4,%ymm6,%ymm2
+ vpand %ymm4,%ymm6,%ymm2
+ vpandn %ymm4,%ymm6,%ymm2
+ vpavgb %ymm4,%ymm6,%ymm2
+ vpavgw %ymm4,%ymm6,%ymm2
+ vpblendw $7,%ymm4,%ymm6,%ymm2
+ vpcmpeqb %ymm4,%ymm6,%ymm2
+ vpcmpeqd %ymm4,%ymm6,%ymm2
+ vpcmpeqq %ymm4,%ymm6,%ymm2
+ vpcmpeqw %ymm4,%ymm6,%ymm2
+ vpcmpgtb %ymm4,%ymm6,%ymm2
+ vpcmpgtd %ymm4,%ymm6,%ymm2
+ vpcmpgtq %ymm4,%ymm6,%ymm2
+ vpcmpgtw %ymm4,%ymm6,%ymm2
+ vphaddd %ymm4,%ymm6,%ymm2
+ vphaddsw %ymm4,%ymm6,%ymm2
+ vphaddw %ymm4,%ymm6,%ymm2
+ vphsubd %ymm4,%ymm6,%ymm2
+ vphsubsw %ymm4,%ymm6,%ymm2
+ vphsubw %ymm4,%ymm6,%ymm2
+ vpmaddubsw %ymm4,%ymm6,%ymm2
+ vpmaddwd %ymm4,%ymm6,%ymm2
+ vpmaxsb %ymm4,%ymm6,%ymm2
+ vpmaxsd %ymm4,%ymm6,%ymm2
+ vpmaxsw %ymm4,%ymm6,%ymm2
+ vpmaxub %ymm4,%ymm6,%ymm2
+ vpmaxud %ymm4,%ymm6,%ymm2
+ vpmaxuw %ymm4,%ymm6,%ymm2
+ vpminsb %ymm4,%ymm6,%ymm2
+ vpminsd %ymm4,%ymm6,%ymm2
+ vpminsw %ymm4,%ymm6,%ymm2
+ vpminub %ymm4,%ymm6,%ymm2
+ vpminud %ymm4,%ymm6,%ymm2
+ vpminuw %ymm4,%ymm6,%ymm2
+ vpmovmskb %ymm4,%ecx
+ vpmovsxbd %xmm4,%ymm6
+ vpmovsxbq %xmm4,%ymm4
+ vpmovsxbw %xmm4,%ymm4
+ vpmovsxdq %xmm4,%ymm4
+ vpmovsxwd %xmm4,%ymm4
+ vpmovsxwq %xmm4,%ymm6
+ vpmovzxbd %xmm4,%ymm6
+ vpmovzxbq %xmm4,%ymm4
+ vpmovzxbw %xmm4,%ymm4
+ vpmovzxdq %xmm4,%ymm4
+ vpmovzxwd %xmm4,%ymm4
+ vpmovzxwq %xmm4,%ymm6
+ vpmuldq %ymm4,%ymm6,%ymm2
+ vpmulhrsw %ymm4,%ymm6,%ymm2
+ vpmulhuw %ymm4,%ymm6,%ymm2
+ vpmulhw %ymm4,%ymm6,%ymm2
+ vpmulld %ymm4,%ymm6,%ymm2
+ vpmullw %ymm4,%ymm6,%ymm2
+ vpmuludq %ymm4,%ymm6,%ymm2
+ vpor %ymm4,%ymm6,%ymm2
+ vpsadbw %ymm4,%ymm6,%ymm2
+ vpshufb %ymm4,%ymm6,%ymm2
+ vpshufd $7,%ymm6,%ymm2
+ vpshufhw $7,%ymm6,%ymm2
+ vpshuflw $7,%ymm6,%ymm2
+ vpsignb %ymm4,%ymm6,%ymm2
+ vpsignd %ymm4,%ymm6,%ymm2
+ vpsignw %ymm4,%ymm6,%ymm2
+ vpslld $7,%ymm6,%ymm2
+ vpslldq $7,%ymm6,%ymm2
+ vpsllq $7,%ymm6,%ymm2
+ vpsllw $7,%ymm6,%ymm2
+ vpsrad $7,%ymm6,%ymm2
+ vpsraw $7,%ymm6,%ymm2
+ vpsrld $7,%ymm6,%ymm2
+ vpsrldq $7,%ymm6,%ymm2
+ vpsrlq $7,%ymm6,%ymm2
+ vpsrlw $7,%ymm6,%ymm2
+ vpsubb %ymm4,%ymm6,%ymm2
+ vpsubd %ymm4,%ymm6,%ymm2
+ vpsubq %ymm4,%ymm6,%ymm2
+ vpsubsb %ymm4,%ymm6,%ymm2
+ vpsubsw %ymm4,%ymm6,%ymm2
+ vpsubusb %ymm4,%ymm6,%ymm2
+ vpsubusw %ymm4,%ymm6,%ymm2
+ vpsubw %ymm4,%ymm6,%ymm2
+ vpunpckhbw %ymm4,%ymm6,%ymm2
+ vpunpckhdq %ymm4,%ymm6,%ymm2
+ vpunpckhqdq %ymm4,%ymm6,%ymm2
+ vpunpckhwd %ymm4,%ymm6,%ymm2
+ vpunpcklbw %ymm4,%ymm6,%ymm2
+ vpunpckldq %ymm4,%ymm6,%ymm2
+ vpunpcklqdq %ymm4,%ymm6,%ymm2
+ vpunpcklwd %ymm4,%ymm6,%ymm2
+ vpxor %ymm4,%ymm6,%ymm2

[H.J. Lu]

The VEX.W bit is ignored by some VEX instructions, aka WIG instructions.
Update x86 disassembler to handle VEX WIG instructions.

* i386-dis.c (VZERO_Fixup): Removed.
(VZERO): Likewise.
(VEX_LEN_0F10_P_1): Likewise.
(VEX_LEN_0F10_P_3): Likewise.
(VEX_LEN_0F11_P_1): Likewise.
(VEX_LEN_0F11_P_3): Likewise.
(VEX_LEN_0F2E_P_0): Likewise.
(VEX_LEN_0F2E_P_2): Likewise.
(VEX_LEN_0F2F_P_0): Likewise.
(VEX_LEN_0F2F_P_2): Likewise.
(VEX_LEN_0F51_P_1): Likewise.
(VEX_LEN_0F51_P_3): Likewise.
(VEX_LEN_0F52_P_1): Likewise.
(VEX_LEN_0F53_P_1): Likewise.
(VEX_LEN_0F58_P_1): Likewise.
(VEX_LEN_0F58_P_3): Likewise.
(VEX_LEN_0F59_P_1): Likewise.
(VEX_LEN_0F59_P_3): Likewise.
(VEX_LEN_0F5A_P_1): Likewise.
(VEX_LEN_0F5A_P_3): Likewise.
(VEX_LEN_0F5C_P_1): Likewise.
(VEX_LEN_0F5C_P_3): Likewise.
(VEX_LEN_0F5D_P_1): Likewise.
(VEX_LEN_0F5D_P_3): Likewise.
(VEX_LEN_0F5E_P_1): Likewise.
(VEX_LEN_0F5E_P_3): Likewise.
(VEX_LEN_0F5F_P_1): Likewise.
(VEX_LEN_0F5F_P_3): Likewise.
(VEX_LEN_0FC2_P_1): Likewise.
(VEX_LEN_0FC2_P_3): Likewise.
(VEX_LEN_0F3A0A_P_2): Likewise.
(VEX_LEN_0F3A0B_P_2): Likewise.
(VEX_W_0F10_P_0): Likewise.
(VEX_W_0F10_P_1): Likewise.
(VEX_W_0F10_P_2): Likewise.
(VEX_W_0F10_P_3): Likewise.
(VEX_W_0F11_P_0): Likewise.
(VEX_W_0F11_P_1): Likewise.
(VEX_W_0F11_P_2): Likewise.
(VEX_W_0F11_P_3): Likewise.
(VEX_W_0F12_P_0_M_0): Likewise.
(VEX_W_0F12_P_0_M_1): Likewise.
(VEX_W_0F12_P_1): Likewise.
(VEX_W_0F12_P_2): Likewise.
(VEX_W_0F12_P_3): Likewise.
(VEX_W_0F13_M_0): Likewise.
(VEX_W_0F14): Likewise.
(VEX_W_0F15): Likewise.
(VEX_W_0F16_P_0_M_0): Likewise.
(VEX_W_0F16_P_0_M_1): Likewise.
(VEX_W_0F16_P_1): Likewise.
(VEX_W_0F16_P_2): Likewise.
(VEX_W_0F17_M_0): Likewise.
(VEX_W_0F28): Likewise.
(VEX_W_0F29): Likewise.
(VEX_W_0F2B_M_0): Likewise.
(VEX_W_0F2E_P_0): Likewise.
(VEX_W_0F2E_P_2): Likewise.
(VEX_W_0F2F_P_0): Likewise.
(VEX_W_0F2F_P_2): Likewise.
(VEX_W_0F50_M_0): Likewise.
(VEX_W_0F51_P_0): Likewise.
(VEX_W_0F51_P_1): Likewise.
(VEX_W_0F51_P_2): Likewise.
(VEX_W_0F51_P_3): Likewise.
(VEX_W_0F52_P_0): Likewise.
(VEX_W_0F52_P_1): Likewise.
(VEX_W_0F53_P_0): Likewise.
(VEX_W_0F53_P_1): Likewise.
(VEX_W_0F58_P_0): Likewise.
(VEX_W_0F58_P_1): Likewise.
(VEX_W_0F58_P_2): Likewise.
(VEX_W_0F58_P_3): Likewise.
(VEX_W_0F59_P_0): Likewise.
(VEX_W_0F59_P_1): Likewise.
(VEX_W_0F59_P_2): Likewise.
(VEX_W_0F59_P_3): Likewise.
(VEX_W_0F5A_P_0): Likewise.
(VEX_W_0F5A_P_1): Likewise.
(VEX_W_0F5A_P_3): Likewise.
(VEX_W_0F5B_P_0): Likewise.
(VEX_W_0F5B_P_1): Likewise.
(VEX_W_0F5B_P_2): Likewise.
(VEX_W_0F5C_P_0): Likewise.
(VEX_W_0F5C_P_1): Likewise.
(VEX_W_0F5C_P_2): Likewise.
(VEX_W_0F5C_P_3): Likewise.
(VEX_W_0F5D_P_0): Likewise.
(VEX_W_0F5D_P_1): Likewise.
(VEX_W_0F5D_P_2): Likewise.
(VEX_W_0F5D_P_3): Likewise.
(VEX_W_0F5E_P_0): Likewise.
(VEX_W_0F5E_P_1): Likewise.
(VEX_W_0F5E_P_2): Likewise.
(VEX_W_0F5E_P_3): Likewise.
(VEX_W_0F5F_P_0): Likewise.
(VEX_W_0F5F_P_1): Likewise.
(VEX_W_0F5F_P_2): Likewise.
(VEX_W_0F5F_P_3): Likewise.
(VEX_W_0F60_P_2): Likewise.
(VEX_W_0F61_P_2): Likewise.
(VEX_W_0F62_P_2): Likewise.
(VEX_W_0F63_P_2): Likewise.
(VEX_W_0F64_P_2): Likewise.
(VEX_W_0F65_P_2): Likewise.
(VEX_W_0F66_P_2): Likewise.
(VEX_W_0F67_P_2): Likewise.
(VEX_W_0F68_P_2): Likewise.
(VEX_W_0F69_P_2): Likewise.
(VEX_W_0F6A_P_2): Likewise.
(VEX_W_0F6B_P_2): Likewise.
(VEX_W_0F6C_P_2): Likewise.
(VEX_W_0F6D_P_2): Likewise.
(VEX_W_0F6F_P_1): Likewise.
(VEX_W_0F6F_P_2): Likewise.
(VEX_W_0F70_P_1): Likewise.
(VEX_W_0F70_P_2): Likewise.
(VEX_W_0F70_P_3): Likewise.
(VEX_W_0F71_R_2_P_2): Likewise.
(VEX_W_0F71_R_4_P_2): Likewise.
(VEX_W_0F71_R_6_P_2): Likewise.
(VEX_W_0F72_R_2_P_2): Likewise.
(VEX_W_0F72_R_4_P_2): Likewise.
(VEX_W_0F72_R_6_P_2): Likewise.
(VEX_W_0F73_R_2_P_2): Likewise.
(VEX_W_0F73_R_3_P_2): Likewise.
(VEX_W_0F73_R_6_P_2): Likewise.
(VEX_W_0F73_R_7_P_2): Likewise.
(VEX_W_0F74_P_2): Likewise.
(VEX_W_0F75_P_2): Likewise.
(VEX_W_0F76_P_2): Likewise.
(VEX_W_0F77_P_0): Likewise.
(VEX_W_0F7C_P_2): Likewise.
(VEX_W_0F7C_P_3): Likewise.
(VEX_W_0F7D_P_2): Likewise.
(VEX_W_0F7D_P_3): Likewise.
(VEX_W_0F7E_P_1): Likewise.
(VEX_W_0F7F_P_1): Likewise.
(VEX_W_0F7F_P_2): Likewise.
(VEX_W_0FAE_R_2_M_0): Likewise.
(VEX_W_0FAE_R_3_M_0): Likewise.
(VEX_W_0FC2_P_0): Likewise.
(VEX_W_0FC2_P_1): Likewise.
(VEX_W_0FC2_P_2): Likewise.
(VEX_W_0FC2_P_3): Likewise.
(VEX_W_0FD0_P_2): Likewise.
(VEX_W_0FD0_P_3): Likewise.
(VEX_W_0FD1_P_2): Likewise.
(VEX_W_0FD2_P_2): Likewise.
(VEX_W_0FD3_P_2): Likewise.
(VEX_W_0FD4_P_2): Likewise.
(VEX_W_0FD5_P_2): Likewise.
(VEX_W_0FD6_P_2): Likewise.
(VEX_W_0FD7_P_2_M_1): Likewise.
(VEX_W_0FD8_P_2): Likewise.
(VEX_W_0FD9_P_2): Likewise.
(VEX_W_0FDA_P_2): Likewise.
(VEX_W_0FDB_P_2): Likewise.
(VEX_W_0FDC_P_2): Likewise.
(VEX_W_0FDD_P_2): Likewise.
(VEX_W_0FDE_P_2): Likewise.
(VEX_W_0FDF_P_2): Likewise.
(VEX_W_0FE0_P_2): Likewise.
(VEX_W_0FE1_P_2): Likewise.
(VEX_W_0FE2_P_2): Likewise.
(VEX_W_0FE3_P_2): Likewise.
(VEX_W_0FE4_P_2): Likewise.
(VEX_W_0FE5_P_2): Likewise.
(VEX_W_0FE6_P_1): Likewise.
(VEX_W_0FE6_P_2): Likewise.
(VEX_W_0FE6_P_3): Likewise.
(VEX_W_0FE7_P_2_M_0): Likewise.
(VEX_W_0FE8_P_2): Likewise.
(VEX_W_0FE9_P_2): Likewise.
(VEX_W_0FEA_P_2): Likewise.
(VEX_W_0FEB_P_2): Likewise.
(VEX_W_0FEC_P_2): Likewise.
(VEX_W_0FED_P_2): Likewise.
(VEX_W_0FEE_P_2): Likewise.
(VEX_W_0FEF_P_2): Likewise.
(VEX_W_0FF0_P_3_M_0): Likewise.
(VEX_W_0FF1_P_2): Likewise.
(VEX_W_0FF2_P_2): Likewise.
(VEX_W_0FF3_P_2): Likewise.
(VEX_W_0FF4_P_2): Likewise.
(VEX_W_0FF5_P_2): Likewise.
(VEX_W_0FF6_P_2): Likewise.
(VEX_W_0FF7_P_2): Likewise.
(VEX_W_0FF8_P_2): Likewise.
(VEX_W_0FF9_P_2): Likewise.
(VEX_W_0FFA_P_2): Likewise.
(VEX_W_0FFB_P_2): Likewise.
(VEX_W_0FFC_P_2): Likewise.
(VEX_W_0FFD_P_2): Likewise.
(VEX_W_0FFE_P_2): Likewise.
(VEX_W_0F3800_P_2): Likewise.
(VEX_W_0F3801_P_2): Likewise.
(VEX_W_0F3802_P_2): Likewise.
(VEX_W_0F3803_P_2): Likewise.
(VEX_W_0F3804_P_2): Likewise.
(VEX_W_0F3805_P_2): Likewise.
(VEX_W_0F3806_P_2): Likewise.
(VEX_W_0F3807_P_2): Likewise.
(VEX_W_0F3808_P_2): Likewise.
(VEX_W_0F3809_P_2): Likewise.
(VEX_W_0F380A_P_2): Likewise.
(VEX_W_0F380B_P_2): Likewise.
(VEX_W_0F3817_P_2): Likewise.
(VEX_W_0F381C_P_2): Likewise.
(VEX_W_0F381D_P_2): Likewise.
(VEX_W_0F381E_P_2): Likewise.
(VEX_W_0F3820_P_2): Likewise.
(VEX_W_0F3821_P_2): Likewise.
(VEX_W_0F3822_P_2): Likewise.
(VEX_W_0F3823_P_2): Likewise.
(VEX_W_0F3824_P_2): Likewise.
(VEX_W_0F3825_P_2): Likewise.
(VEX_W_0F3828_P_2): Likewise.
(VEX_W_0F3829_P_2): Likewise.
(VEX_W_0F382A_P_2_M_0): Likewise.
(VEX_W_0F382B_P_2): Likewise.
(VEX_W_0F3830_P_2): Likewise.
(VEX_W_0F3831_P_2): Likewise.
(VEX_W_0F3832_P_2): Likewise.
(VEX_W_0F3833_P_2): Likewise.
(VEX_W_0F3834_P_2): Likewise.
(VEX_W_0F3835_P_2): Likewise.
(VEX_W_0F3837_P_2): Likewise.
(VEX_W_0F3838_P_2): Likewise.
(VEX_W_0F3839_P_2): Likewise.
(VEX_W_0F383A_P_2): Likewise.
(VEX_W_0F383B_P_2): Likewise.
(VEX_W_0F383C_P_2): Likewise.
(VEX_W_0F383D_P_2): Likewise.
(VEX_W_0F383E_P_2): Likewise.
(VEX_W_0F383F_P_2): Likewise.
(VEX_W_0F3840_P_2): Likewise.
(VEX_W_0F3841_P_2): Likewise.
(VEX_W_0F38DB_P_2): Likewise.
(VEX_W_0F3A08_P_2): Likewise.
(VEX_W_0F3A09_P_2): Likewise.
(VEX_W_0F3A0A_P_2): Likewise.
(VEX_W_0F3A0B_P_2): Likewise.
(VEX_W_0F3A0C_P_2): Likewise.
(VEX_W_0F3A0D_P_2): Likewise.
(VEX_W_0F3A0E_P_2): Likewise.
(VEX_W_0F3A0F_P_2): Likewise.
(VEX_W_0F3A21_P_2): Likewise.
(VEX_W_0F3A40_P_2): Likewise.
(VEX_W_0F3A41_P_2): Likewise.
(VEX_W_0F3A42_P_2): Likewise.
(VEX_W_0F3A62_P_2): Likewise.
(VEX_W_0F3A63_P_2): Likewise.
(VEX_W_0F3ADF_P_2): Likewise.
(VEX_LEN_0F77_P_0): New.
(prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
(vex_table): Update VEX 0F28 and 0F29 entries.
(vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
VEX_LEN_0F3A0B_P_2 entries.
(vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
VEX_W_0F3ADF_P_2 entries.
(mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
---
opcodes/i386-dis.c | 1987 ++++++++------------------------------------
1 file changed, 328 insertions(+), 1659 deletions(-)

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 52521745bc..02bf3404ba 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -95,7 +95,6 @@ static void OP_XMM_VexW (int, int);
static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
-static void VZERO_Fixup (int, int);
static void VCMP_Fixup (int, int);
static void VPCMP_Fixup (int, int);
static void VPCOM_Fixup (int, int);
@@ -442,7 +441,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define XMVexW { OP_XMM_VexW, 0 }
#define XMVexI4 { OP_REG_VexI4, x_mode }
#define PCLMUL { PCLMUL_Fixup, 0 }
-#define VZERO { VZERO_Fixup, 0 }
#define VCMP { VCMP_Fixup, 0 }
#define VPCMP { VPCMP_Fixup, 0 }
#define VPCOM { VPCOM_Fixup, 0 }
@@ -1812,11 +1810,7 @@ enum

enum
{
- VEX_LEN_0F10_P_1 = 0,
- VEX_LEN_0F10_P_3,
- VEX_LEN_0F11_P_1,
- VEX_LEN_0F11_P_3,
- VEX_LEN_0F12_P_0_M_0,
+ VEX_LEN_0F12_P_0_M_0 = 0,
VEX_LEN_0F12_P_0_M_1,
VEX_LEN_0F12_P_2,
VEX_LEN_0F13_M_0,
@@ -1830,10 +1824,6 @@ enum
VEX_LEN_0F2C_P_3,
VEX_LEN_0F2D_P_1,
VEX_LEN_0F2D_P_3,
- VEX_LEN_0F2E_P_0,
- VEX_LEN_0F2E_P_2,
- VEX_LEN_0F2F_P_0,
- VEX_LEN_0F2F_P_2,
VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2,
VEX_LEN_0F42_P_0,
@@ -1850,25 +1840,8 @@ enum
VEX_LEN_0F4A_P_2,
VEX_LEN_0F4B_P_0,
VEX_LEN_0F4B_P_2,
- VEX_LEN_0F51_P_1,
- VEX_LEN_0F51_P_3,
- VEX_LEN_0F52_P_1,
- VEX_LEN_0F53_P_1,
- VEX_LEN_0F58_P_1,
- VEX_LEN_0F58_P_3,
- VEX_LEN_0F59_P_1,
- VEX_LEN_0F59_P_3,
- VEX_LEN_0F5A_P_1,
- VEX_LEN_0F5A_P_3,
- VEX_LEN_0F5C_P_1,
- VEX_LEN_0F5C_P_3,
- VEX_LEN_0F5D_P_1,
- VEX_LEN_0F5D_P_3,
- VEX_LEN_0F5E_P_1,
- VEX_LEN_0F5E_P_3,
- VEX_LEN_0F5F_P_1,
- VEX_LEN_0F5F_P_3,
VEX_LEN_0F6E_P_2,
+ VEX_LEN_0F77_P_0,
VEX_LEN_0F7E_P_1,
VEX_LEN_0F7E_P_2,
VEX_LEN_0F90_P_0,
@@ -1887,8 +1860,6 @@ enum
VEX_LEN_0F99_P_2,
VEX_LEN_0FAE_R_2_M_0,
VEX_LEN_0FAE_R_3_M_0,
- VEX_LEN_0FC2_P_1,
- VEX_LEN_0FC2_P_3,
VEX_LEN_0FC4_P_2,
VEX_LEN_0FC5_P_2,
VEX_LEN_0FD6_P_2,
@@ -1915,8 +1886,6 @@ enum
VEX_LEN_0F3A00_P_2,
VEX_LEN_0F3A01_P_2,
VEX_LEN_0F3A06_P_2,
- VEX_LEN_0F3A0A_P_2,
- VEX_LEN_0F3A0B_P_2,
VEX_LEN_0F3A14_P_2,
VEX_LEN_0F3A15_P_2,
VEX_LEN_0F3A16_P_2,
@@ -1962,35 +1931,7 @@ enum

enum
{
- VEX_W_0F10_P_0 = 0,
- VEX_W_0F10_P_1,
- VEX_W_0F10_P_2,
- VEX_W_0F10_P_3,
- VEX_W_0F11_P_0,
- VEX_W_0F11_P_1,
- VEX_W_0F11_P_2,
- VEX_W_0F11_P_3,
- VEX_W_0F12_P_0_M_0,
- VEX_W_0F12_P_0_M_1,
- VEX_W_0F12_P_1,
- VEX_W_0F12_P_2,
- VEX_W_0F12_P_3,
- VEX_W_0F13_M_0,
- VEX_W_0F14,
- VEX_W_0F15,
- VEX_W_0F16_P_0_M_0,
- VEX_W_0F16_P_0_M_1,
- VEX_W_0F16_P_1,
- VEX_W_0F16_P_2,
- VEX_W_0F17_M_0,
- VEX_W_0F28,
- VEX_W_0F29,
- VEX_W_0F2B_M_0,
- VEX_W_0F2E_P_0,
- VEX_W_0F2E_P_2,
- VEX_W_0F2F_P_0,
- VEX_W_0F2F_P_2,
- VEX_W_0F41_P_0_LEN_1,
+ VEX_W_0F41_P_0_LEN_1 = 0,
VEX_W_0F41_P_2_LEN_1,
VEX_W_0F42_P_0_LEN_1,
VEX_W_0F42_P_2_LEN_1,
@@ -2006,85 +1947,6 @@ enum
VEX_W_0F4A_P_2_LEN_1,
VEX_W_0F4B_P_0_LEN_1,
VEX_W_0F4B_P_2_LEN_1,
- VEX_W_0F50_M_0,
- VEX_W_0F51_P_0,
- VEX_W_0F51_P_1,
- VEX_W_0F51_P_2,
- VEX_W_0F51_P_3,
- VEX_W_0F52_P_0,
- VEX_W_0F52_P_1,
- VEX_W_0F53_P_0,
- VEX_W_0F53_P_1,
- VEX_W_0F58_P_0,
- VEX_W_0F58_P_1,
- VEX_W_0F58_P_2,
- VEX_W_0F58_P_3,
- VEX_W_0F59_P_0,
- VEX_W_0F59_P_1,
- VEX_W_0F59_P_2,
- VEX_W_0F59_P_3,
- VEX_W_0F5A_P_0,
- VEX_W_0F5A_P_1,
- VEX_W_0F5A_P_3,
- VEX_W_0F5B_P_0,
- VEX_W_0F5B_P_1,
- VEX_W_0F5B_P_2,
- VEX_W_0F5C_P_0,
- VEX_W_0F5C_P_1,
- VEX_W_0F5C_P_2,
- VEX_W_0F5C_P_3,
- VEX_W_0F5D_P_0,
- VEX_W_0F5D_P_1,
- VEX_W_0F5D_P_2,
- VEX_W_0F5D_P_3,
- VEX_W_0F5E_P_0,
- VEX_W_0F5E_P_1,
- VEX_W_0F5E_P_2,
- VEX_W_0F5E_P_3,
- VEX_W_0F5F_P_0,
- VEX_W_0F5F_P_1,
- VEX_W_0F5F_P_2,
- VEX_W_0F5F_P_3,
- VEX_W_0F60_P_2,
- VEX_W_0F61_P_2,
- VEX_W_0F62_P_2,
- VEX_W_0F63_P_2,
- VEX_W_0F64_P_2,
- VEX_W_0F65_P_2,
- VEX_W_0F66_P_2,
- VEX_W_0F67_P_2,
- VEX_W_0F68_P_2,
- VEX_W_0F69_P_2,
- VEX_W_0F6A_P_2,
- VEX_W_0F6B_P_2,
- VEX_W_0F6C_P_2,
- VEX_W_0F6D_P_2,
- VEX_W_0F6F_P_1,
- VEX_W_0F6F_P_2,
- VEX_W_0F70_P_1,
- VEX_W_0F70_P_2,
- VEX_W_0F70_P_3,
- VEX_W_0F71_R_2_P_2,
- VEX_W_0F71_R_4_P_2,
- VEX_W_0F71_R_6_P_2,
- VEX_W_0F72_R_2_P_2,
- VEX_W_0F72_R_4_P_2,
- VEX_W_0F72_R_6_P_2,
- VEX_W_0F73_R_2_P_2,
- VEX_W_0F73_R_3_P_2,
- VEX_W_0F73_R_6_P_2,
- VEX_W_0F73_R_7_P_2,
- VEX_W_0F74_P_2,
- VEX_W_0F75_P_2,
- VEX_W_0F76_P_2,
- VEX_W_0F77_P_0,
- VEX_W_0F7C_P_2,
- VEX_W_0F7C_P_3,
- VEX_W_0F7D_P_2,
- VEX_W_0F7D_P_3,
- VEX_W_0F7E_P_1,
- VEX_W_0F7F_P_1,
- VEX_W_0F7F_P_2,
VEX_W_0F90_P_0_LEN_0,
VEX_W_0F90_P_2_LEN_0,
VEX_W_0F91_P_0_LEN_0,
@@ -2099,120 +1961,21 @@ enum
VEX_W_0F98_P_2_LEN_0,
VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0,
- VEX_W_0FAE_R_2_M_0,
- VEX_W_0FAE_R_3_M_0,
- VEX_W_0FC2_P_0,
- VEX_W_0FC2_P_1,
- VEX_W_0FC2_P_2,
- VEX_W_0FC2_P_3,
VEX_W_0FC4_P_2,
VEX_W_0FC5_P_2,
- VEX_W_0FD0_P_2,
- VEX_W_0FD0_P_3,
- VEX_W_0FD1_P_2,
- VEX_W_0FD2_P_2,
- VEX_W_0FD3_P_2,
- VEX_W_0FD4_P_2,
- VEX_W_0FD5_P_2,
- VEX_W_0FD6_P_2,
- VEX_W_0FD7_P_2_M_1,
- VEX_W_0FD8_P_2,
- VEX_W_0FD9_P_2,
- VEX_W_0FDA_P_2,
- VEX_W_0FDB_P_2,
- VEX_W_0FDC_P_2,
- VEX_W_0FDD_P_2,
- VEX_W_0FDE_P_2,
- VEX_W_0FDF_P_2,
- VEX_W_0FE0_P_2,
- VEX_W_0FE1_P_2,
- VEX_W_0FE2_P_2,
- VEX_W_0FE3_P_2,
- VEX_W_0FE4_P_2,
- VEX_W_0FE5_P_2,
- VEX_W_0FE6_P_1,
- VEX_W_0FE6_P_2,
- VEX_W_0FE6_P_3,
- VEX_W_0FE7_P_2_M_0,
- VEX_W_0FE8_P_2,
- VEX_W_0FE9_P_2,
- VEX_W_0FEA_P_2,
- VEX_W_0FEB_P_2,
- VEX_W_0FEC_P_2,
- VEX_W_0FED_P_2,
- VEX_W_0FEE_P_2,
- VEX_W_0FEF_P_2,
- VEX_W_0FF0_P_3_M_0,
- VEX_W_0FF1_P_2,
- VEX_W_0FF2_P_2,
- VEX_W_0FF3_P_2,
- VEX_W_0FF4_P_2,
- VEX_W_0FF5_P_2,
- VEX_W_0FF6_P_2,
- VEX_W_0FF7_P_2,
- VEX_W_0FF8_P_2,
- VEX_W_0FF9_P_2,
- VEX_W_0FFA_P_2,
- VEX_W_0FFB_P_2,
- VEX_W_0FFC_P_2,
- VEX_W_0FFD_P_2,
- VEX_W_0FFE_P_2,
- VEX_W_0F3800_P_2,
- VEX_W_0F3801_P_2,
- VEX_W_0F3802_P_2,
- VEX_W_0F3803_P_2,
- VEX_W_0F3804_P_2,
- VEX_W_0F3805_P_2,
- VEX_W_0F3806_P_2,
- VEX_W_0F3807_P_2,
- VEX_W_0F3808_P_2,
- VEX_W_0F3809_P_2,
- VEX_W_0F380A_P_2,
- VEX_W_0F380B_P_2,
VEX_W_0F380C_P_2,
VEX_W_0F380D_P_2,
VEX_W_0F380E_P_2,
VEX_W_0F380F_P_2,
VEX_W_0F3816_P_2,
- VEX_W_0F3817_P_2,
VEX_W_0F3818_P_2,
VEX_W_0F3819_P_2,
VEX_W_0F381A_P_2_M_0,
- VEX_W_0F381C_P_2,
- VEX_W_0F381D_P_2,
- VEX_W_0F381E_P_2,
- VEX_W_0F3820_P_2,
- VEX_W_0F3821_P_2,
- VEX_W_0F3822_P_2,
- VEX_W_0F3823_P_2,
- VEX_W_0F3824_P_2,
- VEX_W_0F3825_P_2,
- VEX_W_0F3828_P_2,
- VEX_W_0F3829_P_2,
- VEX_W_0F382A_P_2_M_0,
- VEX_W_0F382B_P_2,
VEX_W_0F382C_P_2_M_0,
VEX_W_0F382D_P_2_M_0,
VEX_W_0F382E_P_2_M_0,
VEX_W_0F382F_P_2_M_0,
- VEX_W_0F3830_P_2,
- VEX_W_0F3831_P_2,
- VEX_W_0F3832_P_2,
- VEX_W_0F3833_P_2,
- VEX_W_0F3834_P_2,
- VEX_W_0F3835_P_2,
VEX_W_0F3836_P_2,
- VEX_W_0F3837_P_2,
- VEX_W_0F3838_P_2,
- VEX_W_0F3839_P_2,
- VEX_W_0F383A_P_2,
- VEX_W_0F383B_P_2,
- VEX_W_0F383C_P_2,
- VEX_W_0F383D_P_2,
- VEX_W_0F383E_P_2,
- VEX_W_0F383F_P_2,
- VEX_W_0F3840_P_2,
- VEX_W_0F3841_P_2,
VEX_W_0F3846_P_2,
VEX_W_0F3858_P_2,
VEX_W_0F3859_P_2,
@@ -2220,47 +1983,31 @@ enum
VEX_W_0F3878_P_2,
VEX_W_0F3879_P_2,
VEX_W_0F38CF_P_2,
- VEX_W_0F38DB_P_2,
VEX_W_0F3A00_P_2,
VEX_W_0F3A01_P_2,
VEX_W_0F3A02_P_2,
VEX_W_0F3A04_P_2,
VEX_W_0F3A05_P_2,
VEX_W_0F3A06_P_2,
- VEX_W_0F3A08_P_2,
- VEX_W_0F3A09_P_2,
- VEX_W_0F3A0A_P_2,
- VEX_W_0F3A0B_P_2,
- VEX_W_0F3A0C_P_2,
- VEX_W_0F3A0D_P_2,
- VEX_W_0F3A0E_P_2,
- VEX_W_0F3A0F_P_2,
VEX_W_0F3A14_P_2,
VEX_W_0F3A15_P_2,
VEX_W_0F3A18_P_2,
VEX_W_0F3A19_P_2,
VEX_W_0F3A20_P_2,
- VEX_W_0F3A21_P_2,
VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A31_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0,
VEX_W_0F3A33_P_2_LEN_0,
VEX_W_0F3A38_P_2,
VEX_W_0F3A39_P_2,
- VEX_W_0F3A40_P_2,
- VEX_W_0F3A41_P_2,
- VEX_W_0F3A42_P_2,
VEX_W_0F3A46_P_2,
VEX_W_0F3A48_P_2,
VEX_W_0F3A49_P_2,
VEX_W_0F3A4A_P_2,
VEX_W_0F3A4B_P_2,
VEX_W_0F3A4C_P_2,
- VEX_W_0F3A62_P_2,
- VEX_W_0F3A63_P_2,
VEX_W_0F3ACE_P_2,
VEX_W_0F3ACF_P_2,
- VEX_W_0F3ADF_P_2,

EVEX_W_0F10_P_0,
EVEX_W_0F10_P_1_M_0,
@@ -4888,32 +4635,32 @@ static const struct dis386 prefix_table[][4] = {

/* PREFIX_VEX_0F10 */
{
- { VEX_W_TABLE (VEX_W_0F10_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
- { VEX_W_TABLE (VEX_W_0F10_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
+ { "vmovups", { XM, EXx }, 0 },
+ { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
+ { "vmovupd", { XM, EXx }, 0 },
+ { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F11 */
{
- { VEX_W_TABLE (VEX_W_0F11_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
- { VEX_W_TABLE (VEX_W_0F11_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
+ { "vmovups", { EXxS, XM }, 0 },
+ { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
+ { "vmovupd", { EXxS, XM }, 0 },
+ { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
},

/* PREFIX_VEX_0F12 */
{
{ MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
- { VEX_W_TABLE (VEX_W_0F12_P_1) },
+ { "vmovsldup", { XM, EXx }, 0 },
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
- { VEX_W_TABLE (VEX_W_0F12_P_3) },
+ { "vmovddup", { XM, EXymmq }, 0 },
},

/* PREFIX_VEX_0F16 */
{
{ MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
- { VEX_W_TABLE (VEX_W_0F16_P_1) },
+ { "vmovshdup", { XM, EXx }, 0 },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
},

@@ -4943,16 +4690,16 @@ static const struct dis386 prefix_table[][4] = {

/* PREFIX_VEX_0F2E */
{
- { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
+ { "vucomiss", { XMScalar, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
+ { "vucomisd", { XMScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F2F */
{
- { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
+ { "vcomiss", { XMScalar, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
+ { "vcomisd", { XMScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F41 */
@@ -5013,183 +4760,183 @@ static const struct dis386 prefix_table[][4] = {

/* PREFIX_VEX_0F51 */
{
- { VEX_W_TABLE (VEX_W_0F51_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
- { VEX_W_TABLE (VEX_W_0F51_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
+ { "vsqrtps", { XM, EXx }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vsqrtpd", { XM, EXx }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F52 */
{
- { VEX_W_TABLE (VEX_W_0F52_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
+ { "vrsqrtps", { XM, EXx }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
},

/* PREFIX_VEX_0F53 */
{
- { VEX_W_TABLE (VEX_W_0F53_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
+ { "vrcpps", { XM, EXx }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
},

/* PREFIX_VEX_0F58 */
{
- { VEX_W_TABLE (VEX_W_0F58_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
- { VEX_W_TABLE (VEX_W_0F58_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
+ { "vaddps", { XM, Vex, EXx }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vaddpd", { XM, Vex, EXx }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F59 */
{
- { VEX_W_TABLE (VEX_W_0F59_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
- { VEX_W_TABLE (VEX_W_0F59_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
+ { "vmulps", { XM, Vex, EXx }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vmulpd", { XM, Vex, EXx }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F5A */
{
- { VEX_W_TABLE (VEX_W_0F5A_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
- { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
+ { "vcvtps2pd", { XM, EXxmmq }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F5B */
{
- { VEX_W_TABLE (VEX_W_0F5B_P_0) },
- { VEX_W_TABLE (VEX_W_0F5B_P_1) },
- { VEX_W_TABLE (VEX_W_0F5B_P_2) },
+ { "vcvtdq2ps", { XM, EXx }, 0 },
+ { "vcvttps2dq", { XM, EXx }, 0 },
+ { "vcvtps2dq", { XM, EXx }, 0 },
},

/* PREFIX_VEX_0F5C */
{
- { VEX_W_TABLE (VEX_W_0F5C_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
- { VEX_W_TABLE (VEX_W_0F5C_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
+ { "vsubps", { XM, Vex, EXx }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vsubpd", { XM, Vex, EXx }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F5D */
{
- { VEX_W_TABLE (VEX_W_0F5D_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
- { VEX_W_TABLE (VEX_W_0F5D_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
+ { "vminps", { XM, Vex, EXx }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vminpd", { XM, Vex, EXx }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F5E */
{
- { VEX_W_TABLE (VEX_W_0F5E_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
- { VEX_W_TABLE (VEX_W_0F5E_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
+ { "vdivps", { XM, Vex, EXx }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vdivpd", { XM, Vex, EXx }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F5F */
{
- { VEX_W_TABLE (VEX_W_0F5F_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
- { VEX_W_TABLE (VEX_W_0F5F_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
+ { "vmaxps", { XM, Vex, EXx }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vmaxpd", { XM, Vex, EXx }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},

/* PREFIX_VEX_0F60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F60_P_2) },
+ { "vpunpcklbw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F61_P_2) },
+ { "vpunpcklwd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F62 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F62_P_2) },
+ { "vpunpckldq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F63 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F63_P_2) },
+ { "vpacksswb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F64 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F64_P_2) },
+ { "vpcmpgtb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F65 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F65_P_2) },
+ { "vpcmpgtw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F66 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F66_P_2) },
+ { "vpcmpgtd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F67 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F67_P_2) },
+ { "vpackuswb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F68 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F68_P_2) },
+ { "vpunpckhbw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F69_P_2) },
+ { "vpunpckhwd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6A_P_2) },
+ { "vpunpckhdq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F6B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6B_P_2) },
+ { "vpackssdw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6C_P_2) },
+ { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6D_P_2) },
+ { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F6E */
@@ -5202,128 +4949,128 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F6F */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6F_P_1) },
- { VEX_W_TABLE (VEX_W_0F6F_P_2) },
+ { "vmovdqu", { XM, EXx }, 0 },
+ { "vmovdqa", { XM, EXx }, 0 },
},

/* PREFIX_VEX_0F70 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F70_P_1) },
- { VEX_W_TABLE (VEX_W_0F70_P_2) },
- { VEX_W_TABLE (VEX_W_0F70_P_3) },
+ { "vpshufhw", { XM, EXx, Ib }, 0 },
+ { "vpshufd", { XM, EXx, Ib }, 0 },
+ { "vpshuflw", { XM, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F71_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
+ { "vpsrlw", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F71_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
+ { "vpsraw", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F71_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
+ { "vpsllw", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F72_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
+ { "vpsrld", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F72_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
+ { "vpsrad", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F72_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
+ { "vpslld", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F73_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
+ { "vpsrlq", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F73_REG_3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
+ { "vpsrldq", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F73_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
+ { "vpsllq", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F73_REG_7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
+ { "vpslldq", { Vex, XS, Ib }, 0 },
},

/* PREFIX_VEX_0F74 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F74_P_2) },
+ { "vpcmpeqb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F75 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F75_P_2) },
+ { "vpcmpeqw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F76 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F76_P_2) },
+ { "vpcmpeqd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F77 */
{
- { VEX_W_TABLE (VEX_W_0F77_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
},

/* PREFIX_VEX_0F7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7C_P_2) },
- { VEX_W_TABLE (VEX_W_0F7C_P_3) },
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
+ { "vhaddps", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F7D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7D_P_2) },
- { VEX_W_TABLE (VEX_W_0F7D_P_3) },
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
+ { "vhsubps", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F7E */
@@ -5336,8 +5083,8 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F7F */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7F_P_1) },
- { VEX_W_TABLE (VEX_W_0F7F_P_2) },
+ { "vmovdqu", { EXxS, XM }, 0 },
+ { "vmovdqa", { EXxS, XM }, 0 },
},

/* PREFIX_VEX_0F90 */
@@ -5386,10 +5133,10 @@ static const struct dis386 prefix_table[][4] = {

/* PREFIX_VEX_0FC2 */
{
- { VEX_W_TABLE (VEX_W_0FC2_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
+ { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
+ { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
},

/* PREFIX_VEX_0FC4 */
@@ -5410,43 +5157,43 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD0_P_2) },
- { VEX_W_TABLE (VEX_W_0FD0_P_3) },
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FD1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD1_P_2) },
+ { "vpsrlw", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FD2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD2_P_2) },
+ { "vpsrld", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FD3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD3_P_2) },
+ { "vpsrlq", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FD4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD4_P_2) },
+ { "vpaddq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FD5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD5_P_2) },
+ { "vpmullw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FD6 */
@@ -5467,106 +5214,106 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD8_P_2) },
+ { "vpsubusb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FD9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD9_P_2) },
+ { "vpsubusw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FDA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDA_P_2) },
+ { "vpminub", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FDB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDB_P_2) },
+ { "vpand", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FDC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDC_P_2) },
+ { "vpaddusb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FDD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDD_P_2) },
+ { "vpaddusw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FDE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDE_P_2) },
+ { "vpmaxub", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FDF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDF_P_2) },
+ { "vpandn", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FE0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE0_P_2) },
+ { "vpavgb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FE1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE1_P_2) },
+ { "vpsraw", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FE2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE2_P_2) },
+ { "vpsrad", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FE3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE3_P_2) },
+ { "vpavgw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FE4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE4_P_2) },
+ { "vpmulhuw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FE5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE5_P_2) },
+ { "vpmulhw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FE6 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE6_P_1) },
- { VEX_W_TABLE (VEX_W_0FE6_P_2) },
- { VEX_W_TABLE (VEX_W_0FE6_P_3) },
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
},

/* PREFIX_VEX_0FE7 */
@@ -5580,56 +5327,56 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE8_P_2) },
+ { "vpsubsb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FE9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE9_P_2) },
+ { "vpsubsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FEA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEA_P_2) },
+ { "vpminsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FEB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEB_P_2) },
+ { "vpor", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FEC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEC_P_2) },
+ { "vpaddsb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FED */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FED_P_2) },
+ { "vpaddsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FEE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEE_P_2) },
+ { "vpmaxsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FEF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEF_P_2) },
+ { "vpxor", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FF0 */
@@ -5644,42 +5391,42 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF1_P_2) },
+ { "vpsllw", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FF2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF2_P_2) },
+ { "vpslld", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FF3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF3_P_2) },
+ { "vpsllq", { XM, Vex, EXxmm }, 0 },
},

/* PREFIX_VEX_0FF4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF4_P_2) },
+ { "vpmuludq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FF5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF5_P_2) },
+ { "vpmaddwd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FF6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF6_P_2) },
+ { "vpsadbw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FF7 */
@@ -5693,133 +5440,133 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF8_P_2) },
+ { "vpsubb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FF9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF9_P_2) },
+ { "vpsubw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FFA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFA_P_2) },
+ { "vpsubd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FFB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFB_P_2) },
+ { "vpsubq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FFC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFC_P_2) },
+ { "vpaddb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FFD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFD_P_2) },
+ { "vpaddw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0FFE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFE_P_2) },
+ { "vpaddd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3800 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3800_P_2) },
+ { "vpshufb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3801 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3801_P_2) },
+ { "vphaddw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3802 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3802_P_2) },
+ { "vphaddd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3803 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3803_P_2) },
+ { "vphaddsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3804 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3804_P_2) },
+ { "vpmaddubsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3805 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3805_P_2) },
+ { "vphsubw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3806 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3806_P_2) },
+ { "vphsubd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3807 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3807_P_2) },
+ { "vphsubsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3808 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3808_P_2) },
+ { "vpsignb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3809 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3809_P_2) },
+ { "vpsignw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F380A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380A_P_2) },
+ { "vpsignd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F380B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380B_P_2) },
+ { "vpmulhrsw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F380C */
@@ -5868,7 +5615,7 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3817_P_2) },
+ { "vptest", { XM, EXx }, 0 },
},

/* PREFIX_VEX_0F3818 */
@@ -5896,77 +5643,77 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381C_P_2) },
+ { "vpabsb", { XM, EXx }, 0 },
},

/* PREFIX_VEX_0F381D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381D_P_2) },
+ { "vpabsw", { XM, EXx }, 0 },
},

/* PREFIX_VEX_0F381E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381E_P_2) },
+ { "vpabsd", { XM, EXx }, 0 },
},

/* PREFIX_VEX_0F3820 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3820_P_2) },
+ { "vpmovsxbw", { XM, EXxmmq }, 0 },
},

/* PREFIX_VEX_0F3821 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3821_P_2) },
+ { "vpmovsxbd", { XM, EXxmmqd }, 0 },
},

/* PREFIX_VEX_0F3822 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3822_P_2) },
+ { "vpmovsxbq", { XM, EXxmmdw }, 0 },
},

/* PREFIX_VEX_0F3823 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3823_P_2) },
+ { "vpmovsxwd", { XM, EXxmmq }, 0 },
},

/* PREFIX_VEX_0F3824 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3824_P_2) },
+ { "vpmovsxwq", { XM, EXxmmqd }, 0 },
},

/* PREFIX_VEX_0F3825 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3825_P_2) },
+ { "vpmovsxdq", { XM, EXxmmq }, 0 },
},

/* PREFIX_VEX_0F3828 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3828_P_2) },
+ { "vpmuldq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3829 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3829_P_2) },
+ { "vpcmpeqq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F382A */
@@ -5980,7 +5727,7 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F382B_P_2) },
+ { "vpackusdw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F382C */
@@ -6015,42 +5762,42 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3830_P_2) },
+ { "vpmovzxbw", { XM, EXxmmq }, 0 },
},

/* PREFIX_VEX_0F3831 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3831_P_2) },
+ { "vpmovzxbd", { XM, EXxmmqd }, 0 },
},

/* PREFIX_VEX_0F3832 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3832_P_2) },
+ { "vpmovzxbq", { XM, EXxmmdw }, 0 },
},

/* PREFIX_VEX_0F3833 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3833_P_2) },
+ { "vpmovzxwd", { XM, EXxmmq }, 0 },
},

/* PREFIX_VEX_0F3834 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3834_P_2) },
+ { "vpmovzxwq", { XM, EXxmmqd }, 0 },
},

/* PREFIX_VEX_0F3835 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+ { "vpmovzxdq", { XM, EXxmmq }, 0 },
},

/* PREFIX_VEX_0F3836 */
@@ -6064,70 +5811,70 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3837_P_2) },
+ { "vpcmpgtq", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3838 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3838_P_2) },
+ { "vpminsb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3839 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3839_P_2) },
+ { "vpminsd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F383A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383A_P_2) },
+ { "vpminuw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F383B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383B_P_2) },
+ { "vpminud", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F383C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383C_P_2) },
+ { "vpmaxsb", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F383D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383D_P_2) },
+ { "vpmaxsd", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F383E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383E_P_2) },
+ { "vpmaxuw", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F383F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383F_P_2) },
+ { "vpmaxud", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3840 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3840_P_2) },
+ { "vpmulld", { XM, Vex, EXx }, 0 },
},

/* PREFIX_VEX_0F3841 */
@@ -6578,56 +6325,56 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
+ { "vroundps", { XM, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A09 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
+ { "vroundpd", { XM, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A0A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
+ { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
},

/* PREFIX_VEX_0F3A0B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
+ { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
},

/* PREFIX_VEX_0F3A0C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
+ { "vblendps", { XM, Vex, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A0D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
+ { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A0E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
+ { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A0F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
+ { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A14 */
@@ -6746,7 +6493,7 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
+ { "vdpps", { XM, Vex, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A41 */
@@ -6760,7 +6507,7 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
+ { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},

/* PREFIX_VEX_0F3A44 */
@@ -8674,8 +8421,8 @@ static const struct dis386 vex_table[][256] = {
{ PREFIX_TABLE (PREFIX_VEX_0F11) },
{ PREFIX_TABLE (PREFIX_VEX_0F12) },
{ MOD_TABLE (MOD_VEX_0F13) },
- { VEX_W_TABLE (VEX_W_0F14) },
- { VEX_W_TABLE (VEX_W_0F15) },
+ { "vunpcklpX", { XM, Vex, EXx }, 0 },
+ { "vunpckhpX", { XM, Vex, EXx }, 0 },
{ PREFIX_TABLE (PREFIX_VEX_0F16) },
{ MOD_TABLE (MOD_VEX_0F17) },
/* 18 */
@@ -8697,8 +8444,8 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
- { VEX_W_TABLE (VEX_W_0F28) },
- { VEX_W_TABLE (VEX_W_0F29) },
+ { "vmovapX", { XM, EXx }, 0 },
+ { "vmovapX", { EXxS, XM }, 0 },
{ PREFIX_TABLE (PREFIX_VEX_0F2A) },
{ MOD_TABLE (MOD_VEX_0F2B) },
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
@@ -9528,68 +9275,44 @@ static const struct dis386 vex_table[][256] = {
#include "i386-dis-evex.h"
#undef NEED_OPCODE_TABLE
static const struct dis386 vex_len_table[][2] = {
- /* VEX_LEN_0F10_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F10_P_1) },
- { VEX_W_TABLE (VEX_W_0F10_P_1) },
- },
-
- /* VEX_LEN_0F10_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F10_P_3) },
- { VEX_W_TABLE (VEX_W_0F10_P_3) },
- },
-
- /* VEX_LEN_0F11_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F11_P_1) },
- { VEX_W_TABLE (VEX_W_0F11_P_1) },
- },
-
- /* VEX_LEN_0F11_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F11_P_3) },
- { VEX_W_TABLE (VEX_W_0F11_P_3) },
- },
-
/* VEX_LEN_0F12_P_0_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
+ { "vmovlps", { XM, Vex128, EXq }, 0 },
},

/* VEX_LEN_0F12_P_0_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
+ { "vmovhlps", { XM, Vex128, EXq }, 0 },
},

/* VEX_LEN_0F12_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_2) },
+ { "vmovlpd", { XM, Vex128, EXq }, 0 },
},

/* VEX_LEN_0F13_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F13_M_0) },
+ { "vmovlpX", { EXq, XM }, 0 },
},

/* VEX_LEN_0F16_P_0_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
+ { "vmovhps", { XM, Vex128, EXq }, 0 },
},

/* VEX_LEN_0F16_P_0_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
+ { "vmovlhps", { XM, Vex128, EXq }, 0 },
},

/* VEX_LEN_0F16_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_2) },
+ { "vmovhpd", { XM, Vex128, EXq }, 0 },
},

/* VEX_LEN_0F17_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F17_M_0) },
+ { "vmovhpX", { EXq, XM }, 0 },
},

/* VEX_LEN_0F2A_P_1 */
@@ -9628,30 +9351,6 @@ static const struct dis386 vex_len_table[][2] = {
{ "vcvtsd2si", { Gv, EXqScalar }, 0 },
},

- /* VEX_LEN_0F2E_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F2E_P_0) },
- { VEX_W_TABLE (VEX_W_0F2E_P_0) },
- },
-
- /* VEX_LEN_0F2E_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F2E_P_2) },
- { VEX_W_TABLE (VEX_W_0F2E_P_2) },
- },
-
- /* VEX_LEN_0F2F_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F2F_P_0) },
- { VEX_W_TABLE (VEX_W_0F2F_P_0) },
- },
-
- /* VEX_LEN_0F2F_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F2F_P_2) },
- { VEX_W_TABLE (VEX_W_0F2F_P_2) },
- },
-
/* VEX_LEN_0F41_P_0 */
{
{ Bad_Opcode },
@@ -9731,182 +9430,80 @@ static const struct dis386 vex_len_table[][2] = {
{ VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
},

- /* VEX_LEN_0F51_P_1 */
+ /* VEX_LEN_0F6E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F51_P_1) },
- { VEX_W_TABLE (VEX_W_0F51_P_1) },
+ { "vmovK", { XMScalar, Edq }, 0 },
+ { "vmovK", { XMScalar, Edq }, 0 },
},

- /* VEX_LEN_0F51_P_3 */
+ /* VEX_LEN_0F77_P_1 */
{
- { VEX_W_TABLE (VEX_W_0F51_P_3) },
- { VEX_W_TABLE (VEX_W_0F51_P_3) },
+ { "vzeroupper", { XX }, 0 },
+ { "vzeroall", { XX }, 0 },
},

- /* VEX_LEN_0F52_P_1 */
+ /* VEX_LEN_0F7E_P_1 */
{
- { VEX_W_TABLE (VEX_W_0F52_P_1) },
- { VEX_W_TABLE (VEX_W_0F52_P_1) },
+ { "vmovq", { XMScalar, EXqScalar }, 0 },
},

- /* VEX_LEN_0F53_P_1 */
+ /* VEX_LEN_0F7E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F53_P_1) },
- { VEX_W_TABLE (VEX_W_0F53_P_1) },
+ { "vmovK", { Edq, XMScalar }, 0 },
+ { "vmovK", { Edq, XMScalar }, 0 },
},

- /* VEX_LEN_0F58_P_1 */
+ /* VEX_LEN_0F90_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F58_P_1) },
- { VEX_W_TABLE (VEX_W_0F58_P_1) },
+ { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
},

- /* VEX_LEN_0F58_P_3 */
+ /* VEX_LEN_0F90_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F58_P_3) },
- { VEX_W_TABLE (VEX_W_0F58_P_3) },
+ { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
},

- /* VEX_LEN_0F59_P_1 */
+ /* VEX_LEN_0F91_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F59_P_1) },
- { VEX_W_TABLE (VEX_W_0F59_P_1) },
+ { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
},

- /* VEX_LEN_0F59_P_3 */
+ /* VEX_LEN_0F91_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F59_P_3) },
- { VEX_W_TABLE (VEX_W_0F59_P_3) },
+ { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
},

- /* VEX_LEN_0F5A_P_1 */
+ /* VEX_LEN_0F92_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F5A_P_1) },
- { VEX_W_TABLE (VEX_W_0F5A_P_1) },
+ { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
},

- /* VEX_LEN_0F5A_P_3 */
+ /* VEX_LEN_0F92_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F5A_P_3) },
- { VEX_W_TABLE (VEX_W_0F5A_P_3) },
+ { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
},

- /* VEX_LEN_0F5C_P_1 */
+ /* VEX_LEN_0F92_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F5C_P_1) },
- { VEX_W_TABLE (VEX_W_0F5C_P_1) },
+ { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
},

- /* VEX_LEN_0F5C_P_3 */
+ /* VEX_LEN_0F93_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F5C_P_3) },
- { VEX_W_TABLE (VEX_W_0F5C_P_3) },
+ { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
},

- /* VEX_LEN_0F5D_P_1 */
+ /* VEX_LEN_0F93_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F5D_P_1) },
- { VEX_W_TABLE (VEX_W_0F5D_P_1) },
+ { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
},

- /* VEX_LEN_0F5D_P_3 */
+ /* VEX_LEN_0F93_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F5D_P_3) },
- { VEX_W_TABLE (VEX_W_0F5D_P_3) },
+ { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
},

- /* VEX_LEN_0F5E_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5E_P_1) },
- { VEX_W_TABLE (VEX_W_0F5E_P_1) },
- },
-
- /* VEX_LEN_0F5E_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5E_P_3) },
- { VEX_W_TABLE (VEX_W_0F5E_P_3) },
- },
-
- /* VEX_LEN_0F5F_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5F_P_1) },
- { VEX_W_TABLE (VEX_W_0F5F_P_1) },
- },
-
- /* VEX_LEN_0F5F_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5F_P_3) },
- { VEX_W_TABLE (VEX_W_0F5F_P_3) },
- },
-
- /* VEX_LEN_0F6E_P_2 */
- {
- { "vmovK", { XMScalar, Edq }, 0 },
- { "vmovK", { XMScalar, Edq }, 0 },
- },
-
- /* VEX_LEN_0F7E_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F7E_P_1) },
- },
-
- /* VEX_LEN_0F7E_P_2 */
- {
- { "vmovK", { Edq, XMScalar }, 0 },
- { "vmovK", { Edq, XMScalar }, 0 },
- },
-
- /* VEX_LEN_0F90_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
- },
-
- /* VEX_LEN_0F90_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
- },
-
- /* VEX_LEN_0F91_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
- },
-
- /* VEX_LEN_0F91_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
- },
-
- /* VEX_LEN_0F92_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
- },
-
- /* VEX_LEN_0F92_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
- },
-
- /* VEX_LEN_0F92_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
- },
-
- /* VEX_LEN_0F93_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
- },
-
- /* VEX_LEN_0F93_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
- },
-
- /* VEX_LEN_0F93_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
- },
-
- /* VEX_LEN_0F98_P_0 */
+ /* VEX_LEN_0F98_P_0 */
{
{ VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
},
@@ -9928,24 +9525,12 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0FAE_R_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
+ { "vldmxcsr", { Md }, 0 },
},

/* VEX_LEN_0FAE_R_3_M_0 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
- },
-
- /* VEX_LEN_0FC2_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- },
-
- /* VEX_LEN_0FC2_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ { "vstmxcsr", { Md }, 0 },
},

/* VEX_LEN_0FC4_P_2 */
@@ -9960,12 +9545,12 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0FD6_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ { "vmovq", { EXqScalarS, XMScalar }, 0 },
},

/* VEX_LEN_0FF7_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF7_P_2) },
+ { "vmaskmovdqu", { XM, XS }, 0 },
},

/* VEX_LEN_0F3816_P_2 */
@@ -9994,7 +9579,7 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0F3841_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3841_P_2) },
+ { "vphminposuw", { XM, EXx }, 0 },
},

/* VEX_LEN_0F385A_P_2_M_0 */
@@ -10005,7 +9590,7 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0F38DB_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
+ { "vaesimc", { XM, EXx }, 0 },
},

/* VEX_LEN_0F38F2_P_0 */
@@ -10086,18 +9671,6 @@ static const struct dis386 vex_len_table[][2] = {
{ VEX_W_TABLE (VEX_W_0F3A06_P_2) },
},

- /* VEX_LEN_0F3A0A_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- },
-
- /* VEX_LEN_0F3A0B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- },
-
/* VEX_LEN_0F3A14_P_2 */
{
{ VEX_W_TABLE (VEX_W_0F3A14_P_2) },
@@ -10137,7 +9710,7 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0F3A21_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
+ { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
},

/* VEX_LEN_0F3A22_P_2 */
@@ -10179,7 +9752,7 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0F3A41_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
+ { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
},

/* VEX_LEN_0F3A46_P_2 */
@@ -10200,12 +9773,12 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0F3A62_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
+ { "vpcmpistrm", { XM, EXx, Ib }, 0 },
},

/* VEX_LEN_0F3A63_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
+ { "vpcmpistri", { XM, EXx, Ib }, 0 },
},

/* VEX_LEN_0F3A6A_P_2 */
@@ -10250,7 +9823,7 @@ static const struct dis386 vex_len_table[][2] = {

/* VEX_LEN_0F3ADF_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
+ { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
},

/* VEX_LEN_0F3AF0_P_3 */
@@ -10312,118 +9885,6 @@ static const struct dis386 vex_len_table[][2] = {
};

static const struct dis386 vex_w_table[][2] = {
- {
- /* VEX_W_0F10_P_0 */
- { "vmovups", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F10_P_1 */
- { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F10_P_2 */
- { "vmovupd", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F10_P_3 */
- { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F11_P_0 */
- { "vmovups", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F11_P_1 */
- { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
- },
- {
- /* VEX_W_0F11_P_2 */
- { "vmovupd", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F11_P_3 */
- { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
- },
- {
- /* VEX_W_0F12_P_0_M_0 */
- { "vmovlps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F12_P_0_M_1 */
- { "vmovhlps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F12_P_1 */
- { "vmovsldup", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F12_P_2 */
- { "vmovlpd", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F12_P_3 */
- { "vmovddup", { XM, EXymmq }, 0 },
- },
- {
- /* VEX_W_0F13_M_0 */
- { "vmovlpX", { EXq, XM }, 0 },
- },
- {
- /* VEX_W_0F14 */
- { "vunpcklpX", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F15 */
- { "vunpckhpX", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F16_P_0_M_0 */
- { "vmovhps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F16_P_0_M_1 */
- { "vmovlhps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F16_P_1 */
- { "vmovshdup", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F16_P_2 */
- { "vmovhpd", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F17_M_0 */
- { "vmovhpX", { EXq, XM }, 0 },
- },
- {
- /* VEX_W_0F28 */
- { "vmovapX", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F29 */
- { "vmovapX", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F2B_M_0 */
- { "vmovntpX", { Mx, XM }, 0 },
- },
- {
- /* VEX_W_0F2E_P_0 */
- { "vucomiss", { XMScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F2E_P_2 */
- { "vucomisd", { XMScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F2F_P_0 */
- { "vcomiss", { XMScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F2F_P_2 */
- { "vcomisd", { XMScalar, EXqScalar }, 0 },
- },
{
/* VEX_W_0F41_P_0_LEN_1 */
{ MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
@@ -10455,715 +9916,127 @@ static const struct dis386 vex_w_table[][2] = {
{ MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
},
{
- /* VEX_W_0F45_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
- },
- {
- /* VEX_W_0F45_P_2_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
- },
- {
- /* VEX_W_0F46_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
- },
- {
- /* VEX_W_0F46_P_2_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
- },
- {
- /* VEX_W_0F47_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
- },
- {
- /* VEX_W_0F47_P_2_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
- },
- {
- /* VEX_W_0F4A_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
- },
- {
- /* VEX_W_0F4A_P_2_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
- },
- {
- /* VEX_W_0F4B_P_0_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
- { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
- },
- {
- /* VEX_W_0F4B_P_2_LEN_1 */
- { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
- },
- {
- /* VEX_W_0F50_M_0 */
- { "vmovmskpX", { Gdq, XS }, 0 },
- },
- {
- /* VEX_W_0F51_P_0 */
- { "vsqrtps", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F51_P_1 */
- { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F51_P_2 */
- { "vsqrtpd", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F51_P_3 */
- { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F52_P_0 */
- { "vrsqrtps", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F52_P_1 */
- { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F53_P_0 */
- { "vrcpps", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F53_P_1 */
- { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F58_P_0 */
- { "vaddps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F58_P_1 */
- { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F58_P_2 */
- { "vaddpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F58_P_3 */
- { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F59_P_0 */
- { "vmulps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F59_P_1 */
- { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F59_P_2 */
- { "vmulpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F59_P_3 */
- { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5A_P_0 */
- { "vcvtps2pd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F5A_P_1 */
- { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5A_P_3 */
- { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5B_P_0 */
- { "vcvtdq2ps", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F5B_P_1 */
- { "vcvttps2dq", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F5B_P_2 */
- { "vcvtps2dq", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F5C_P_0 */
- { "vsubps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5C_P_1 */
- { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5C_P_2 */
- { "vsubpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5C_P_3 */
- { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5D_P_0 */
- { "vminps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5D_P_1 */
- { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5D_P_2 */
- { "vminpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5D_P_3 */
- { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5E_P_0 */
- { "vdivps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5E_P_1 */
- { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5E_P_2 */
- { "vdivpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5E_P_3 */
- { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5F_P_0 */
- { "vmaxps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5F_P_1 */
- { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5F_P_2 */
- { "vmaxpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5F_P_3 */
- { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F60_P_2 */
- { "vpunpcklbw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F61_P_2 */
- { "vpunpcklwd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F62_P_2 */
- { "vpunpckldq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F63_P_2 */
- { "vpacksswb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F64_P_2 */
- { "vpcmpgtb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F65_P_2 */
- { "vpcmpgtw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F66_P_2 */
- { "vpcmpgtd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F67_P_2 */
- { "vpackuswb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F68_P_2 */
- { "vpunpckhbw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F69_P_2 */
- { "vpunpckhwd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6A_P_2 */
- { "vpunpckhdq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6B_P_2 */
- { "vpackssdw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6C_P_2 */
- { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6D_P_2 */
- { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6F_P_1 */
- { "vmovdqu", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F6F_P_2 */
- { "vmovdqa", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F70_P_1 */
- { "vpshufhw", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F70_P_2 */
- { "vpshufd", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F70_P_3 */
- { "vpshuflw", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F71_R_2_P_2 */
- { "vpsrlw", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F71_R_4_P_2 */
- { "vpsraw", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F71_R_6_P_2 */
- { "vpsllw", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F72_R_2_P_2 */
- { "vpsrld", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F72_R_4_P_2 */
- { "vpsrad", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F72_R_6_P_2 */
- { "vpslld", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_2_P_2 */
- { "vpsrlq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_3_P_2 */
- { "vpsrldq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_6_P_2 */
- { "vpsllq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_7_P_2 */
- { "vpslldq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F74_P_2 */
- { "vpcmpeqb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F75_P_2 */
- { "vpcmpeqw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F76_P_2 */
- { "vpcmpeqd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F77_P_0 */
- { "", { VZERO }, 0 },
- },
- {
- /* VEX_W_0F7C_P_2 */
- { "vhaddpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7C_P_3 */
- { "vhaddps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7D_P_2 */
- { "vhsubpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7D_P_3 */
- { "vhsubps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7E_P_1 */
- { "vmovq", { XMScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F7F_P_1 */
- { "vmovdqu", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F7F_P_2 */
- { "vmovdqa", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F90_P_0_LEN_0 */
- { "kmovw", { MaskG, MaskE }, 0 },
- { "kmovq", { MaskG, MaskE }, 0 },
- },
- {
- /* VEX_W_0F90_P_2_LEN_0 */
- { "kmovb", { MaskG, MaskBDE }, 0 },
- { "kmovd", { MaskG, MaskBDE }, 0 },
- },
- {
- /* VEX_W_0F91_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F91_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F92_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F92_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F92_P_3_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
- },
- {
- /* VEX_W_0F93_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F93_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F93_P_3_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
- },
- {
- /* VEX_W_0F98_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F98_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F99_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F99_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
- },
- {
- /* VEX_W_0FAE_R_2_M_0 */
- { "vldmxcsr", { Md }, 0 },
- },
- {
- /* VEX_W_0FAE_R_3_M_0 */
- { "vstmxcsr", { Md }, 0 },
- },
- {
- /* VEX_W_0FC2_P_0 */
- { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC2_P_1 */
- { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC2_P_2 */
- { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC2_P_3 */
- { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC4_P_2 */
- { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
- },
- {
- /* VEX_W_0FC5_P_2 */
- { "vpextrw", { Gdq, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0FD0_P_2 */
- { "vaddsubpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD0_P_3 */
- { "vaddsubps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD1_P_2 */
- { "vpsrlw", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FD2_P_2 */
- { "vpsrld", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FD3_P_2 */
- { "vpsrlq", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FD4_P_2 */
- { "vpaddq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD5_P_2 */
- { "vpmullw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD6_P_2 */
- { "vmovq", { EXqScalarS, XMScalar }, 0 },
- },
- {
- /* VEX_W_0FD7_P_2_M_1 */
- { "vpmovmskb", { Gdq, XS }, 0 },
- },
- {
- /* VEX_W_0FD8_P_2 */
- { "vpsubusb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD9_P_2 */
- { "vpsubusw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDA_P_2 */
- { "vpminub", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDB_P_2 */
- { "vpand", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDC_P_2 */
- { "vpaddusb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDD_P_2 */
- { "vpaddusw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDE_P_2 */
- { "vpmaxub", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDF_P_2 */
- { "vpandn", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE0_P_2 */
- { "vpavgb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE1_P_2 */
- { "vpsraw", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FE2_P_2 */
- { "vpsrad", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FE3_P_2 */
- { "vpavgw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE4_P_2 */
- { "vpmulhuw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE5_P_2 */
- { "vpmulhw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE6_P_1 */
- { "vcvtdq2pd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0FE6_P_2 */
- { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
- },
- {
- /* VEX_W_0FE6_P_3 */
- { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
- },
- {
- /* VEX_W_0FE7_P_2_M_0 */
- { "vmovntdq", { Mx, XM }, 0 },
- },
- {
- /* VEX_W_0FE8_P_2 */
- { "vpsubsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE9_P_2 */
- { "vpsubsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEA_P_2 */
- { "vpminsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEB_P_2 */
- { "vpor", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEC_P_2 */
- { "vpaddsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FED_P_2 */
- { "vpaddsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEE_P_2 */
- { "vpmaxsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEF_P_2 */
- { "vpxor", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FF0_P_3_M_0 */
- { "vlddqu", { XM, M }, 0 },
- },
- {
- /* VEX_W_0FF1_P_2 */
- { "vpsllw", { XM, Vex, EXxmm }, 0 },
+ /* VEX_W_0F45_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
},
{
- /* VEX_W_0FF2_P_2 */
- { "vpslld", { XM, Vex, EXxmm }, 0 },
+ /* VEX_W_0F45_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
},
{
- /* VEX_W_0FF3_P_2 */
- { "vpsllq", { XM, Vex, EXxmm }, 0 },
+ /* VEX_W_0F46_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
},
{
- /* VEX_W_0FF4_P_2 */
- { "vpmuludq", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F46_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
},
{
- /* VEX_W_0FF5_P_2 */
- { "vpmaddwd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F47_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
},
{
- /* VEX_W_0FF6_P_2 */
- { "vpsadbw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F47_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
},
{
- /* VEX_W_0FF7_P_2 */
- { "vmaskmovdqu", { XM, XS }, 0 },
+ /* VEX_W_0F4A_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
},
{
- /* VEX_W_0FF8_P_2 */
- { "vpsubb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F4A_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
},
{
- /* VEX_W_0FF9_P_2 */
- { "vpsubw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F4B_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
},
{
- /* VEX_W_0FFA_P_2 */
- { "vpsubd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F4B_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
},
{
- /* VEX_W_0FFB_P_2 */
- { "vpsubq", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F90_P_0_LEN_0 */
+ { "kmovw", { MaskG, MaskE }, 0 },
+ { "kmovq", { MaskG, MaskE }, 0 },
},
{
- /* VEX_W_0FFC_P_2 */
- { "vpaddb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F90_P_2_LEN_0 */
+ { "kmovb", { MaskG, MaskBDE }, 0 },
+ { "kmovd", { MaskG, MaskBDE }, 0 },
},
{
- /* VEX_W_0FFD_P_2 */
- { "vpaddw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F91_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
},
{
- /* VEX_W_0FFE_P_2 */
- { "vpaddd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F91_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
},
{
- /* VEX_W_0F3800_P_2 */
- { "vpshufb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F92_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
},
{
- /* VEX_W_0F3801_P_2 */
- { "vphaddw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F92_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
},
{
- /* VEX_W_0F3802_P_2 */
- { "vphaddd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F92_P_3_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
},
{
- /* VEX_W_0F3803_P_2 */
- { "vphaddsw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F93_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
},
{
- /* VEX_W_0F3804_P_2 */
- { "vpmaddubsw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F93_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
},
{
- /* VEX_W_0F3805_P_2 */
- { "vphsubw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F93_P_3_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
},
{
- /* VEX_W_0F3806_P_2 */
- { "vphsubd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F98_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
},
{
- /* VEX_W_0F3807_P_2 */
- { "vphsubsw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F98_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
},
{
- /* VEX_W_0F3808_P_2 */
- { "vpsignb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F99_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
},
{
- /* VEX_W_0F3809_P_2 */
- { "vpsignw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F99_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
},
{
- /* VEX_W_0F380A_P_2 */
- { "vpsignd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0FC4_P_2 */
+ { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
},
{
- /* VEX_W_0F380B_P_2 */
- { "vpmulhrsw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0FC5_P_2 */
+ { "vpextrw", { Gdq, XS, Ib }, 0 },
},
{
/* VEX_W_0F380C_P_2 */
@@ -11185,10 +10058,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3816_P_2 */
{ "vpermps", { XM, Vex, EXx }, 0 },
},
- {
- /* VEX_W_0F3817_P_2 */
- { "vptest", { XM, EXx }, 0 },
- },
{
/* VEX_W_0F3818_P_2 */
{ "vbroadcastss", { XM, EXxmm_md }, 0 },
@@ -11201,58 +10070,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F381A_P_2_M_0 */
{ "vbroadcastf128", { XM, Mxmm }, 0 },
},
- {
- /* VEX_W_0F381C_P_2 */
- { "vpabsb", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F381D_P_2 */
- { "vpabsw", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F381E_P_2 */
- { "vpabsd", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F3820_P_2 */
- { "vpmovsxbw", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3821_P_2 */
- { "vpmovsxbd", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3822_P_2 */
- { "vpmovsxbq", { XM, EXxmmdw }, 0 },
- },
- {
- /* VEX_W_0F3823_P_2 */
- { "vpmovsxwd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3824_P_2 */
- { "vpmovsxwq", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3825_P_2 */
- { "vpmovsxdq", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3828_P_2 */
- { "vpmuldq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3829_P_2 */
- { "vpcmpeqq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F382A_P_2_M_0 */
- { "vmovntdqa", { XM, Mx }, 0 },
- },
- {
- /* VEX_W_0F382B_P_2 */
- { "vpackusdw", { XM, Vex, EXx }, 0 },
- },
{
/* VEX_W_0F382C_P_2_M_0 */
{ "vmaskmovps", { XM, Vex, Mx }, 0 },
@@ -11269,78 +10086,10 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F382F_P_2_M_0 */
{ "vmaskmovpd", { Mx, Vex, XM }, 0 },
},
- {
- /* VEX_W_0F3830_P_2 */
- { "vpmovzxbw", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3831_P_2 */
- { "vpmovzxbd", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3832_P_2 */
- { "vpmovzxbq", { XM, EXxmmdw }, 0 },
- },
- {
- /* VEX_W_0F3833_P_2 */
- { "vpmovzxwd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3834_P_2 */
- { "vpmovzxwq", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3835_P_2 */
- { "vpmovzxdq", { XM, EXxmmq }, 0 },
- },
{
/* VEX_W_0F3836_P_2 */
{ "vpermd", { XM, Vex, EXx }, 0 },
},
- {
- /* VEX_W_0F3837_P_2 */
- { "vpcmpgtq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3838_P_2 */
- { "vpminsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3839_P_2 */
- { "vpminsd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383A_P_2 */
- { "vpminuw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383B_P_2 */
- { "vpminud", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383C_P_2 */
- { "vpmaxsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383D_P_2 */
- { "vpmaxsd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383E_P_2 */
- { "vpmaxuw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383F_P_2 */
- { "vpmaxud", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3840_P_2 */
- { "vpmulld", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3841_P_2 */
- { "vphminposuw", { XM, EXx }, 0 },
- },
{
/* VEX_W_0F3846_P_2 */
{ "vpsravd", { XM, Vex, EXx }, 0 },
@@ -11369,10 +10118,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F38CF_P_2 */
{ "vgf2p8mulb", { XM, Vex, EXx }, 0 },
},
- {
- /* VEX_W_0F38DB_P_2 */
- { "vaesimc", { XM, EXx }, 0 },
- },
{
/* VEX_W_0F3A00_P_2 */
{ Bad_Opcode },
@@ -11399,38 +10144,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3A06_P_2 */
{ "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3A08_P_2 */
- { "vroundps", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A09_P_2 */
- { "vroundpd", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0A_P_2 */
- { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0B_P_2 */
- { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0C_P_2 */
- { "vblendps", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0D_P_2 */
- { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0E_P_2 */
- { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0F_P_2 */
- { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
- },
{
/* VEX_W_0F3A14_P_2 */
{ "vpextrb", { Edqb, XM, Ib }, 0 },
@@ -11451,10 +10164,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3A20_P_2 */
{ "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
},
- {
- /* VEX_W_0F3A21_P_2 */
- { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
- },
{
/* VEX_W_0F3A30_P_2_LEN_0 */
{ MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
@@ -11483,18 +10192,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3A39_P_2 */
{ "vextracti128", { EXxmm, XM, Ib }, 0 },
},
- {
- /* VEX_W_0F3A40_P_2 */
- { "vdpps", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A41_P_2 */
- { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A42_P_2 */
- { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
- },
{
/* VEX_W_0F3A46_P_2 */
{ "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
@@ -11521,14 +10218,6 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F3A4C_P_2 */
{ "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- {
- /* VEX_W_0F3A62_P_2 */
- { "vpcmpistrm", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A63_P_2 */
- { "vpcmpistri", { XM, EXx, Ib }, 0 },
- },
{
/* VEX_W_0F3ACE_P_2 */
{ Bad_Opcode },
@@ -11539,10 +10228,6 @@ static const struct dis386 vex_w_table[][2] = {
{ Bad_Opcode },
{ "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3ADF_P_2 */
- { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
- },
#define NEED_VEX_W_TABLE
#include "i386-dis-evex.h"
#undef NEED_VEX_W_TABLE
@@ -11903,7 +10588,7 @@ static const struct dis386 mod_table[][2] = {
},
{
/* MOD_VEX_0F2B */
- { VEX_W_TABLE (VEX_W_0F2B_M_0) },
+ { "vmovntpX", { Mx, XM }, 0 },
},
{
/* MOD_VEX_W_0_0F41_P_0_LEN_1 */
@@ -12063,7 +10748,7 @@ static const struct dis386 mod_table[][2] = {
{
/* MOD_VEX_0F50 */
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F50_M_0) },
+ { "vmovmskpX", { Gdq, XS }, 0 },
},
{
/* MOD_VEX_0F71_REG_2 */
@@ -12226,15 +10911,15 @@ static const struct dis386 mod_table[][2] = {
{
/* MOD_VEX_0FD7_PREFIX_2 */
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
+ { "vpmovmskb", { Gdq, XS }, 0 },
},
{
/* MOD_VEX_0FE7_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
+ { "vmovntdq", { Mx, XM }, 0 },
},
{
/* MOD_VEX_0FF0_PREFIX_3 */
- { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
+ { "vlddqu", { XM, M }, 0 },
},
{
/* MOD_VEX_0F381A_PREFIX_2 */
@@ -12242,7 +10927,7 @@ static const struct dis386 mod_table[][2] = {
},
{
/* MOD_VEX_0F382A_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
+ { "vmovntdqa", { XM, Mx }, 0 },
},
{
/* MOD_VEX_0F382C_PREFIX_2 */
@@ -17626,22 +16311,6 @@ OP_XMM_Vex (int bytemode, int sizeflag)
OP_XMM (bytemode, sizeflag);
}

-static void
-VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- switch (vex.length)
- {
- case 128:
- mnemonicendp = stpcpy (obuf, "vzeroupper");
- break;
- case 256:
- mnemonicendp = stpcpy (obuf, "vzeroall");
- break;
- default:
- abort ();
- }
-}
-
static struct op vex_cmp_op[] =
{
{ STRING_COMMA_LEN ("eq") },

[Jan Beulich]

Post by H.J. Lu
The VEX.Wbit is ignored by some VEX instructions, aka WIG instructions.
This patch set does
1. Update disassembler for WIG VEX instructions.
2. Add -mvexwig=[0|1] assembler option to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
x86: Update disassembler for VexWIG
x86: Add -mvexwig=[0|1] option to assembler

LGTM, FWIW (minus the previously discussed missing revert, but I
realize I won't be able to convince you).

Jan

[H.J. Lu]

Post by Jan Beulich

Post by H.J. Lu
The VEX.Wbit is ignored by some VEX instructions, aka WIG instructions.
This patch set does
1. Update disassembler for WIG VEX instructions.
2. Add -mvexwig=[0|1] assembler option to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
x86: Update disassembler for VexWIG
x86: Add -mvexwig=[0|1] option to assembler

LGTM, FWIW (minus the previously discussed missing revert, but I
realize I won't be able to convince you).

I can be convinced with testcases.