Committed.
R.
Post by Sudakshina Dasrb9971.patch
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 13fe700d5fecfab70d4ccd379c259a1e2c6bd711..0020edf81e6206b2d6d4ae4c4973d1b7e687d930 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8787,6 +8787,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
AARCH64_ARCH_NONE},
+ {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 009a379ce755e1a046589dc98528c1e79aac7e2f..4941c57c48113676cfbdd9ae38b691d468692179 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -187,6 +187,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Execution and Data and Prediction instructions.
@item @code{rng} @tab ARMv8.5-A @tab No
@tab Enable ARMv8.5-A random number instructions.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/ssbs-illegal1.d b/gas/testsuite/gas/aarch64/ssbs-illegal1.d
new file mode 100644
index 0000000000000000000000000000000000000000..b7c1519e2134dbfb6b68e81b5b71043c79dff85e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs-illegal1.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+ssbs --defsym ERROR1=1
+#source: ssbs.s
+#error-output: ssbs-illegal1.l
diff --git a/gas/testsuite/gas/aarch64/ssbs-illegal1.l b/gas/testsuite/gas/aarch64/ssbs-illegal1.l
new file mode 100644
index 0000000000000000000000000000000000000000..74a8b748b1f71989a91f72be250f98dea8aa8c5a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs-illegal1.l
@@ -0,0 +1,15 @@
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#2'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#3'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#4'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#5'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#6'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#7'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#8'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#9'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#10'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#11'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#12'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#13'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#14'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 1 -- `msr ssbs,#15'
diff --git a/gas/testsuite/gas/aarch64/ssbs-illegal2.d b/gas/testsuite/gas/aarch64/ssbs-illegal2.d
new file mode 100644
index 0000000000000000000000000000000000000000..a0674cd004225ee1dc7ddc0fcd6e4e3a313597e7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs-illegal2.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a --defsym ERROR2=1
+#source: ssbs.s
+#error-output: ssbs-illegal2.l
diff --git a/gas/testsuite/gas/aarch64/ssbs-illegal2.l b/gas/testsuite/gas/aarch64/ssbs-illegal2.l
new file mode 100644
index 0000000000000000000000000000000000000000..5443b9a38697570627d693fa42e5e5a84e4bc77e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs-illegal2.l
@@ -0,0 +1,6 @@
+[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'ssbs'
+[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'ssbs'
+[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'ssbs'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'ssbs'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'ssbs'
diff --git a/gas/testsuite/gas/aarch64/ssbs.s b/gas/testsuite/gas/aarch64/ssbs.s
new file mode 100644
index 0000000000000000000000000000000000000000..3938d4535a96f43d607c14b806dc479c45f2b724
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs.s
@@ -0,0 +1,31 @@
+/* Test SSBS. */
+ .ifdef SUCCESS
+ msr ssbs, #1
+ msr ssbs, #0
+
+ .irp N,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+ msr ssbs, x\N
+ mrs x\N, ssbs
+ .endr
+
+ .irp N,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+ msr ssbs, x\N
+ mrs x\N, ssbs
+ .endr
+ .endif
+
+ /* Constant >1 Failure. */
+ .ifdef ERROR1
+ .irp N,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+ msr ssbs, #\N
+ .endr
+ .endif
+
+ /* No +ssbs Failure. */
+ .ifdef ERROR2
+ msr ssbs, #0
+ msr ssbs, #1
+ msr ssbs, x6
+ mrs x25, ssbs
+ .endif
diff --git a/gas/testsuite/gas/aarch64/ssbs1.d b/gas/testsuite/gas/aarch64/ssbs1.d
new file mode 100644
index 0000000000000000000000000000000000000000..daeda76b45b8105b8431e8f881ecaca826d48b53
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs1.d
@@ -0,0 +1,73 @@
+#source: ssbs.s
+#objdump: -dr
+#as: -march=armv8-a+ssbs --defsym SUCCESS=1
+
+.*: file format .*
+
+
+.*: d503413f msr ssbs, #0x1
+.*: d503403f msr ssbs, #0x0
+.*: d51b42c0 msr ssbs, x0
+.*: d53b42c0 mrs x0, ssbs
+.*: d51b42c1 msr ssbs, x1
+.*: d53b42c1 mrs x1, ssbs
+.*: d51b42c2 msr ssbs, x2
+.*: d53b42c2 mrs x2, ssbs
+.*: d51b42c3 msr ssbs, x3
+.*: d53b42c3 mrs x3, ssbs
+.*: d51b42c4 msr ssbs, x4
+.*: d53b42c4 mrs x4, ssbs
+.*: d51b42c5 msr ssbs, x5
+.*: d53b42c5 mrs x5, ssbs
+.*: d51b42c6 msr ssbs, x6
+.*: d53b42c6 mrs x6, ssbs
+.*: d51b42c7 msr ssbs, x7
+.*: d53b42c7 mrs x7, ssbs
+.*: d51b42c8 msr ssbs, x8
+.*: d53b42c8 mrs x8, ssbs
+.*: d51b42c9 msr ssbs, x9
+.*: d53b42c9 mrs x9, ssbs
+.*: d51b42ca msr ssbs, x10
+.*: d53b42ca mrs x10, ssbs
+.*: d51b42cb msr ssbs, x11
+.*: d53b42cb mrs x11, ssbs
+.*: d51b42cc msr ssbs, x12
+.*: d53b42cc mrs x12, ssbs
+.*: d51b42cd msr ssbs, x13
+.*: d53b42cd mrs x13, ssbs
+.*: d51b42ce msr ssbs, x14
+.*: d53b42ce mrs x14, ssbs
+.*: d51b42cf msr ssbs, x15
+.*: d53b42cf mrs x15, ssbs
+.*: d51b42d0 msr ssbs, x16
+.*: d53b42d0 mrs x16, ssbs
+.*: d51b42d1 msr ssbs, x17
+.*: d53b42d1 mrs x17, ssbs
+.*: d51b42d2 msr ssbs, x18
+.*: d53b42d2 mrs x18, ssbs
+.*: d51b42d3 msr ssbs, x19
+.*: d53b42d3 mrs x19, ssbs
+.*: d51b42d4 msr ssbs, x20
+.*: d53b42d4 mrs x20, ssbs
+.*: d51b42d5 msr ssbs, x21
+.*: d53b42d5 mrs x21, ssbs
+.*: d51b42d6 msr ssbs, x22
+.*: d53b42d6 mrs x22, ssbs
+.*: d51b42d7 msr ssbs, x23
+.*: d53b42d7 mrs x23, ssbs
+.*: d51b42d8 msr ssbs, x24
+.*: d53b42d8 mrs x24, ssbs
+.*: d51b42d9 msr ssbs, x25
+.*: d53b42d9 mrs x25, ssbs
+.*: d51b42da msr ssbs, x26
+.*: d53b42da mrs x26, ssbs
+.*: d51b42db msr ssbs, x27
+.*: d53b42db mrs x27, ssbs
+.*: d51b42dc msr ssbs, x28
+.*: d53b42dc mrs x28, ssbs
+.*: d51b42dd msr ssbs, x29
+.*: d53b42dd mrs x29, ssbs
+.*: d51b42de msr ssbs, x30
+.*: d53b42de mrs x30, ssbs
diff --git a/gas/testsuite/gas/aarch64/ssbs2.d b/gas/testsuite/gas/aarch64/ssbs2.d
new file mode 100644
index 0000000000000000000000000000000000000000..0027026b0f41899961563bffb48b55fd22768164
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ssbs2.d
@@ -0,0 +1,73 @@
+#source: ssbs.s
+#objdump: -dr
+#as: -march=armv8.5-a --defsym SUCCESS=1
+
+.*: file format .*
+
+
+.*: d503413f msr ssbs, #0x1
+.*: d503403f msr ssbs, #0x0
+.*: d51b42c0 msr ssbs, x0
+.*: d53b42c0 mrs x0, ssbs
+.*: d51b42c1 msr ssbs, x1
+.*: d53b42c1 mrs x1, ssbs
+.*: d51b42c2 msr ssbs, x2
+.*: d53b42c2 mrs x2, ssbs
+.*: d51b42c3 msr ssbs, x3
+.*: d53b42c3 mrs x3, ssbs
+.*: d51b42c4 msr ssbs, x4
+.*: d53b42c4 mrs x4, ssbs
+.*: d51b42c5 msr ssbs, x5
+.*: d53b42c5 mrs x5, ssbs
+.*: d51b42c6 msr ssbs, x6
+.*: d53b42c6 mrs x6, ssbs
+.*: d51b42c7 msr ssbs, x7
+.*: d53b42c7 mrs x7, ssbs
+.*: d51b42c8 msr ssbs, x8
+.*: d53b42c8 mrs x8, ssbs
+.*: d51b42c9 msr ssbs, x9
+.*: d53b42c9 mrs x9, ssbs
+.*: d51b42ca msr ssbs, x10
+.*: d53b42ca mrs x10, ssbs
+.*: d51b42cb msr ssbs, x11
+.*: d53b42cb mrs x11, ssbs
+.*: d51b42cc msr ssbs, x12
+.*: d53b42cc mrs x12, ssbs
+.*: d51b42cd msr ssbs, x13
+.*: d53b42cd mrs x13, ssbs
+.*: d51b42ce msr ssbs, x14
+.*: d53b42ce mrs x14, ssbs
+.*: d51b42cf msr ssbs, x15
+.*: d53b42cf mrs x15, ssbs
+.*: d51b42d0 msr ssbs, x16
+.*: d53b42d0 mrs x16, ssbs
+.*: d51b42d1 msr ssbs, x17
+.*: d53b42d1 mrs x17, ssbs
+.*: d51b42d2 msr ssbs, x18
+.*: d53b42d2 mrs x18, ssbs
+.*: d51b42d3 msr ssbs, x19
+.*: d53b42d3 mrs x19, ssbs
+.*: d51b42d4 msr ssbs, x20
+.*: d53b42d4 mrs x20, ssbs
+.*: d51b42d5 msr ssbs, x21
+.*: d53b42d5 mrs x21, ssbs
+.*: d51b42d6 msr ssbs, x22
+.*: d53b42d6 mrs x22, ssbs
+.*: d51b42d7 msr ssbs, x23
+.*: d53b42d7 mrs x23, ssbs
+.*: d51b42d8 msr ssbs, x24
+.*: d53b42d8 mrs x24, ssbs
+.*: d51b42d9 msr ssbs, x25
+.*: d53b42d9 mrs x25, ssbs
+.*: d51b42da msr ssbs, x26
+.*: d53b42da mrs x26, ssbs
+.*: d51b42db msr ssbs, x27
+.*: d53b42db mrs x27, ssbs
+.*: d51b42dc msr ssbs, x28
+.*: d53b42dc mrs x28, ssbs
+.*: d51b42dd msr ssbs, x29
+.*: d53b42dd mrs x29, ssbs
+.*: d51b42de msr ssbs, x30
+.*: d53b42de mrs x30, ssbs
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 877a9284b6e37d581e5fcb456648c3644a7501ed..294cde6a5a4906a120a579529080f416d0e99940 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -82,6 +82,8 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
/* ID_PFR2 instructions. */
#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
+/* SSBS mechanism enabled. */
+#define AARCH64_FEATURE_SSBS 0x800000000000ULL
/* Architectures are the sum of the base and extensions. */
@@ -115,7 +117,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_CVADP \
| AARCH64_FEATURE_BTI \
| AARCH64_FEATURE_SCXTNUM \
- | AARCH64_FEATURE_ID_PFR2)
+ | AARCH64_FEATURE_ID_PFR2 \
+ | AARCH64_FEATURE_SSBS)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 29973b5c928ceeda38ff1b172d53c2be17ec600b..fdc617aabade6b055fbbbfb22124f48826eac88c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2470,9 +2470,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
/* MSR UAO, #uimm4
MSR PAN, #uimm4
+ MSR SSBS,#uimm4
The immediate must be #0 or #1. */
if ((opnd->pstatefield == 0x03 /* UAO. */
|| opnd->pstatefield == 0x04 /* PAN. */
+ || opnd->pstatefield == 0x19 /* SSBS. */
|| opnd->pstatefield == 0x1a) /* DIT. */
&& opnds[1].imm.value > 1)
{
@@ -3689,6 +3691,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "pan", CPEN_(0,C2,3), F_ARCHEXT },
{ "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
{ "nzcv", CPEN_(3,C2,0), 0 },
+ { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
{ "fpcr", CPEN_(3,C4,0), 0 },
{ "fpsr", CPEN_(3,C4,1), 0 },
{ "dspsr_el0", CPEN_(3,C5,0), 0 },
@@ -4109,6 +4112,11 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
return FALSE;
+ /* SSBS. Values are from aarch64_sys_regs. */
+ if (reg->value == CPEN_(3,C2,6)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
+ return FALSE;
+
/* Virtualization host extensions: system registers. */
if ((reg->value == CPENC (3, 4, C2, C0, 1)
|| reg->value == CPENC (3, 4, C13, C0, 1)
@@ -4321,6 +4329,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
{ "daifclr", 0x1f, 0 },
{ "pan", 0x04, F_ARCHEXT },
{ "uao", 0x03, F_ARCHEXT },
+ { "ssbs", 0x19, F_ARCHEXT },
{ "dit", 0x1a, F_ARCHEXT },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@@ -4342,6 +4351,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
+ /* SSBS. Values are from aarch64_pstatefields. */
+ if (reg->value == 0x19
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
+ return FALSE;
+
/* DIT. Values are from aarch64_pstatefields. */
if (reg->value == 0x1a
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))