Discussion:
Binutils/gas/ld port for RISC-V
(too old to reply)
Andrew Waterman
2016-10-11 23:46:05 UTC
Permalink
We'd like to submit for inclusion in Binutils a port for the RISC-V
architecture. The port suffices to build a substantial body of software
(including Linux and some 2,000 Fedora packages); so, while it is doubtlessly
not complete, we think it is far enough along to start the upstreaming process.

This port targets Version 2.0 of the RV32I and RV64I base user ISAs, and the
five standard extensions M, A, F, D, and C, all of which are frozen and will
not change over time. It also targets Version 1.9.1 of the RISC-V Privileged
Architectures, which we expect to change somewhat before being standardized
some time in 2017.

The RISC-V community and the 50-some member companies of the RISC-V Foundation
are quite eager to have a single, standard Binutils port. We thank you in
advance for your help in this process and for your feedback on the software
contribution itself.

These patches build on top of 8f1a8fc4df2244f548d55fbecce20b7cd6f90e16, the
latest commit in binutils-gdb.
Andrew Waterman
2016-10-11 23:46:08 UTC
Permalink
---
gdb/config/riscv/linux.mh | 30 ++
gdb/riscv-linux-nat.c | 77 +++
gdb/riscv-linux-tdep.c | 83 +++
gdb/riscv-linux-tdep.h | 30 ++
gdb/riscv-tdep.c | 1293 +++++++++++++++++++++++++++++++++++++++++++++
gdb/riscv-tdep.h | 101 ++++
include/gdb/sim-riscv.h | 98 ++++
7 files changed, 1712 insertions(+)
create mode 100644 gdb/config/riscv/linux.mh
create mode 100644 gdb/riscv-linux-nat.c
create mode 100644 gdb/riscv-linux-tdep.c
create mode 100644 gdb/riscv-linux-tdep.h
create mode 100644 gdb/riscv-tdep.c
create mode 100644 gdb/riscv-tdep.h
create mode 100644 include/gdb/sim-riscv.h

diff --git a/gdb/config/riscv/linux.mh b/gdb/config/riscv/linux.mh
new file mode 100644
index 0000000..f68f371
--- /dev/null
+++ b/gdb/config/riscv/linux.mh
@@ -0,0 +1,30 @@
+# Host: RISC-V based machine running GNU/Linux
+#
+# Copyright (C) 2015 Free Software Foundation, Inc.
+# Contributed by Albert Ou <***@sifive.com>.
+#
+# This file is part of GDB.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+NAT_FILE= config/nm-linux.h
+NATDEPFILES= inf-ptrace.o fork-child.o riscv-linux-nat.o \
+ proc-service.o linux-thread-db.o linux-nat.o linux-fork.o \
+ linux-procfs.o linux-ptrace.o linux-osdata.o linux-waitpid.o \
+ linux-namespaces.o linux-personality.o
+NAT_CDEPS = $(srcdir)/proc-service.list
+
+# The dynamically loaded libthread_db needs access to symbols in the
+# gdb executable.
+LOADLIBES= -ldl $(RDYNAMIC)
diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c
new file mode 100644
index 0000000..6accb7a
--- /dev/null
+++ b/gdb/riscv-linux-nat.c
@@ -0,0 +1,77 @@
+/* Native-dependent code for GNU/Linux RISC-V.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+ Contributed by Albert Ou <***@sifive.com>.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "defs.h"
+
+#include "inferior.h"
+#include "regcache.h"
+
+#include <sys/ptrace.h>
+#include "gregset.h"
+
+#include "riscv-tdep.h"
+#include "riscv-linux-tdep.h"
+
+/* Transfering the general-purpose registers between GDB, inferiors
+ and core files. */
+
+/* Fill GDB's register cache with the general-purpose register values
+ in *GREGSETP. */
+
+void
+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
+{
+ regcache_supply_regset (&riscv_linux_gregset, regcache, -1,
+ (const gdb_byte *) gregsetp,
+ (RISCV_NGREG));
+}
+
+/* Fill register REGNUM (if it is a general-purpose register) in
+ *GREGSETP with the value in GDB's register cache. If REGNUM is -1,
+ do this for all registers. */
+
+void
+fill_gregset (const struct regcache *regcache,
+ gdb_gregset_t *gregsetp, int regno)
+{
+ regcache_collect_regset (&riscv_linux_gregset, regcache,
+ regno, (gdb_byte *) gregsetp,
+ (RISCV_NGREG));
+}
+
+/* Transfering floating-point registers between GDB, inferiors and cores. */
+
+/* Fill GDB's register cache with the floating-point and SSE register
+ values in *FPREGSETP. */
+
+void
+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
+{
+}
+
+/* Fill register REGNUM (if it is a floating-point or SSE register) in
+ *FPREGSETP with the value in GDB's register cache. If REGNUM is
+ -1, do this for all registers. */
+
+void
+fill_fpregset (const struct regcache *regcache,
+ gdb_fpregset_t *fpregsetp, int regnum)
+{
+}
diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
new file mode 100644
index 0000000..b66860c
--- /dev/null
+++ b/gdb/riscv-linux-tdep.c
@@ -0,0 +1,83 @@
+/* Target-dependent code for GNU/Linux RISC-V.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+ Contributed by Albert Ou <***@sifive.com>.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "defs.h"
+
+#include "gdbarch.h"
+#include "osabi.h"
+#include "linux-tdep.h"
+#include "solib-svr4.h"
+#include "glibc-tdep.h"
+
+#include "riscv-tdep.h"
+#include "riscv-linux-tdep.h"
+
+#include "regcache.h"
+#include "regset.h"
+
+static const struct regcache_map_entry riscv_linux_gregmap[] =
+{
+ { 1, RISCV_PC_REGNUM, 0 },
+ { 31, RISCV_RA_REGNUM, 0 }, /* x1 to x31 */
+ { 0 }
+};
+
+const struct regset riscv_linux_gregset =
+{
+ riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset
+};
+
+static void
+riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
+ iterate_over_regset_sections_cb *cb,
+ void *cb_data,
+ const struct regcache *regcache)
+{
+ cb (".reg", (RISCV_NGREG * riscv_isa_regsize (gdbarch)),
+ &riscv_linux_gregset, NULL, cb_data);
+}
+
+static void
+riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+{
+ linux_init_abi (info, gdbarch);
+
+ /* GNU/Linux uses SVR4-style shared libraries. */
+ /* FIXME: This '0' should actually be a check to see if we're on
+ rv32, but I can't figure out how to hook that up (it's in
+ gdbarch_tdep, which we don't have here). */
+ set_solib_svr4_fetch_link_map_offsets
+ (gdbarch, (0) ?
+ svr4_ilp32_fetch_link_map_offsets :
+ svr4_lp64_fetch_link_map_offsets);
+
+ set_gdbarch_iterate_over_regset_sections
+ (gdbarch, riscv_linux_iterate_over_regset_sections);
+}
+
+/* Provide a prototype to silence -Wmissing-prototypes. */
+extern initialize_file_ftype _initialize_riscv_linux_tdep;
+
+void
+_initialize_riscv_linux_tdep (void)
+{
+ gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
+ riscv_linux_init_abi);
+}
diff --git a/gdb/riscv-linux-tdep.h b/gdb/riscv-linux-tdep.h
new file mode 100644
index 0000000..d5758ca
--- /dev/null
+++ b/gdb/riscv-linux-tdep.h
@@ -0,0 +1,30 @@
+/* Target-dependent header for GNU/Linux RISC-V.
+
+ Copyright (C) 2015 Free Software Foundation, Inc.
+ Contributed by Albert Ou <***@sifive.com>.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef RISCV_LINUX_TDEP_H
+#define RISCV_LINUX_TDEP_H
+
+#include "regset.h"
+
+#define RISCV_NGREG (32)
+
+extern const struct regset riscv_linux_gregset;
+
+#endif
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
new file mode 100644
index 0000000..d788e33
--- /dev/null
+++ b/gdb/riscv-tdep.c
@@ -0,0 +1,1293 @@
+/* Target-dependent code for the RISC-V architecture, for GDB.
+
+ Copyright (C) 1988-2015 Free Software Foundation, Inc.
+
+ Contributed by Alessandro Forin(***@cs.cmu.edu) at CMU
+ and by Per Bothner(***@cs.wisc.edu) at U.Wisconsin
+ and by Todd Snyder <***@bluespec.com>
+ and by Mike Frysinger <***@gentoo.org>.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "defs.h"
+#include "frame.h"
+#include "inferior.h"
+#include "symtab.h"
+#include "value.h"
+#include "gdbcmd.h"
+#include "language.h"
+#include "gdbcore.h"
+#include "symfile.h"
+#include "objfiles.h"
+#include "gdbtypes.h"
+#include "target.h"
+#include "arch-utils.h"
+#include "regcache.h"
+#include "osabi.h"
+#include "riscv-tdep.h"
+#include "block.h"
+#include "reggroups.h"
+#include "opcode/riscv.h"
+#include "elf/riscv.h"
+#include "elf-bfd.h"
+#include "symcat.h"
+#include "sim-regno.h"
+#include "gdb/sim-riscv.h"
+#include "dis-asm.h"
+#include "frame-unwind.h"
+#include "frame-base.h"
+#include "trad-frame.h"
+#include "infcall.h"
+#include "floatformat.h"
+#include "remote.h"
+#include "target-descriptions.h"
+#include "dwarf2-frame.h"
+#include "user-regs.h"
+#include "valprint.h"
+#include "opcode/riscv-opc.h"
+#include <algorithm>
+
+struct riscv_frame_cache
+{
+ CORE_ADDR base;
+ struct trad_frame_saved_reg *saved_regs;
+};
+
+static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
+{
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
+ "pc",
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+};
+
+struct register_alias
+{
+ const char *name;
+ int regnum;
+};
+
+static const struct register_alias riscv_register_aliases[] =
+{
+ { "zero", 0 },
+ { "ra", 1 },
+ { "sp", 2 },
+ { "gp", 3 },
+ { "tp", 4 },
+ { "t0", 5 },
+ { "t1", 6 },
+ { "t2", 7 },
+ { "fp", 8 },
+ { "s0", 8 },
+ { "s1", 9 },
+ { "a0", 10 },
+ { "a1", 11 },
+ { "a2", 12 },
+ { "a3", 13 },
+ { "a4", 14 },
+ { "a5", 15 },
+ { "a6", 16 },
+ { "a7", 17 },
+ { "s2", 18 },
+ { "s3", 19 },
+ { "s4", 20 },
+ { "s5", 21 },
+ { "s6", 22 },
+ { "s7", 23 },
+ { "s8", 24 },
+ { "s9", 25 },
+ { "s10", 26 },
+ { "s11", 27 },
+ { "t3", 28 },
+ { "t4", 29 },
+ { "t5", 30 },
+ { "t6", 31 },
+ /* pc is 32. */
+ { "ft0", 33 },
+ { "ft1", 34 },
+ { "ft2", 35 },
+ { "ft3", 36 },
+ { "ft4", 37 },
+ { "ft5", 38 },
+ { "ft6", 39 },
+ { "ft7", 40 },
+ { "fs0", 41 },
+ { "fs1", 42 },
+ { "fa0", 43 },
+ { "fa1", 44 },
+ { "fa2", 45 },
+ { "fa3", 46 },
+ { "fa4", 47 },
+ { "fa5", 48 },
+ { "fa6", 49 },
+ { "fa7", 50 },
+ { "fs2", 51 },
+ { "fs3", 52 },
+ { "fs4", 53 },
+ { "fs5", 54 },
+ { "fs6", 55 },
+ { "fs7", 56 },
+ { "fs8", 57 },
+ { "fs9", 58 },
+ { "fs10", 59 },
+ { "fs11", 60 },
+ { "ft8", 61 },
+ { "ft9", 62 },
+ { "ft10", 63 },
+ { "ft11", 64 },
+#define DECLARE_CSR(name, num) { #name, (num) + 65 },
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+};
+
+static const gdb_byte *
+riscv_breakpoint_from_pc (struct gdbarch *gdbarch,
+ CORE_ADDR *bp_addr,
+ int *bp_size)
+{
+ /* TODO: Support C.EBREAK for compressed (16-bit) insns. */
+ /* TODO: Support NOPs for >=6 byte insns. */
+ static const gdb_byte sbreak_insn[] = { 0x73, 0x00, 0x10, 0x00, };
+
+ *bp_size = 4;
+
+ return sbreak_insn;
+}
+
+static void
+riscv_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *kindptr)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ riscv_breakpoint_from_pc (gdbarch, pcptr, kindptr);
+}
+
+static struct value *
+value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
+{
+ const int *reg_p = (const int *)baton;
+
+ return value_of_register (*reg_p, frame);
+}
+
+static const char *
+register_name (struct gdbarch *gdbarch,
+ int regnum,
+ int prefer_alias)
+{
+ int i;
+ static char buf[20];
+
+ if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return tdesc_register_name (gdbarch, regnum);
+ /* Prefer to use the alias. */
+ if (prefer_alias &&
+ regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
+ {
+ for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
+ if (regnum == riscv_register_aliases[i].regnum)
+ return riscv_register_aliases[i].name;
+ }
+
+ if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
+ return riscv_gdb_reg_names[regnum];
+
+ if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
+ {
+ sprintf(buf, "csr%d", regnum - RISCV_FIRST_CSR_REGNUM);
+ return buf;
+ }
+
+ if (regnum == RISCV_PRIV_REGNUM)
+ {
+ return "priv";
+ }
+
+ return NULL;
+}
+
+static const char *
+riscv_register_name (struct gdbarch *gdbarch,
+ int regnum)
+{
+ return register_name(gdbarch, regnum, 0);
+}
+
+static void
+riscv_extract_return_value (struct type *type,
+ struct regcache *regs,
+ gdb_byte *dst,
+ int regnum)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regs);
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ int regsize = riscv_isa_regsize (gdbarch);
+ bfd_byte *valbuf = dst;
+ int len = TYPE_LENGTH (type);
+ ULONGEST tmp;
+
+ gdb_assert (len <= 2 * regsize);
+
+ while (len > 0)
+ {
+ regcache_cooked_read_unsigned (regs, regnum++, &tmp);
+ store_unsigned_integer (valbuf, std::min (regsize, len), byte_order, tmp);
+ len -= regsize;
+ valbuf += regsize;
+ }
+}
+
+/* Write into appropriate registers a function return value of type
+ TYPE, given in virtual format. */
+
+static void
+riscv_store_return_value (struct type *type,
+ struct regcache *regs,
+ const gdb_byte *src,
+ int regnum)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regs);
+ int regsize = riscv_isa_regsize (gdbarch);
+ const bfd_byte *valbuf = src;
+
+ /* Integral values greater than one word are stored in consecutive
+ registers starting with R0. This will always be a multiple of
+ the register size. */
+
+ int len = TYPE_LENGTH (type);
+
+ gdb_assert (len <= 2 * regsize);
+
+ while (len > 0)
+ {
+ regcache_cooked_write (regs, regnum++, valbuf);
+ len -= regsize;
+ valbuf += regsize;
+ }
+}
+
+static enum return_value_convention
+riscv_return_value (struct gdbarch *gdbarch,
+ struct value *function,
+ struct type *type,
+ struct regcache *regcache,
+ gdb_byte *readbuf,
+ const gdb_byte *writebuf)
+{
+ enum type_code rv_type = TYPE_CODE (type);
+ unsigned int rv_size = TYPE_LENGTH (type);
+ int fp, regnum;
+ ULONGEST tmp;
+
+ /* Paragraph on return values taken from RISC-V specification (post v2.0):
+
+ Values are returned from functions in integer registers a0 and a1 and
+ floating-point registers fa0 and fa1. Floating-point values are returned
+ in floating-point registers only if they are primitives or members of a
+ struct consisting of only one or two floating-point values. Other return
+ values that fit into two pointer-words are returned in a0 and a1. Larger
+ return values are passed entirely in memory; the caller allocates this
+ memory region and passes a pointer to it as an implicit first parameter to
+ the callee. */
+
+ /* Deal with struct/unions first that are passed via memory. */
+ if (rv_size > 2 * riscv_isa_regsize (gdbarch))
+ {
+ if (readbuf || writebuf)
+ regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, &tmp);
+ if (readbuf)
+ read_memory (tmp, readbuf, rv_size);
+ if (writebuf)
+ write_memory (tmp, writebuf, rv_size);
+ return RETURN_VALUE_ABI_RETURNS_ADDRESS;
+ }
+
+ /* Are we dealing with a floating point value? */
+ fp = 0;
+ if (rv_type == TYPE_CODE_FLT)
+ fp = 1;
+ else if (rv_type == TYPE_CODE_STRUCT || rv_type == TYPE_CODE_UNION)
+ {
+ unsigned int rv_fields = TYPE_NFIELDS (type);
+
+ if (rv_fields == 1)
+ {
+ struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
+ if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
+ fp = 1;
+ }
+ else if (rv_fields == 2)
+ {
+ struct type *fieldtype0 = TYPE_FIELD_TYPE (type, 0);
+ struct type *fieldtype1 = TYPE_FIELD_TYPE (type, 1);
+
+ if (TYPE_CODE (check_typedef (fieldtype0)) == TYPE_CODE_FLT
+ && TYPE_CODE (check_typedef (fieldtype1)) == TYPE_CODE_FLT)
+ fp = 1;
+ }
+ }
+
+ /* Handle return value in a register. */
+ regnum = fp ? RISCV_FA0_REGNUM : RISCV_A0_REGNUM;
+
+ if (readbuf)
+ riscv_extract_return_value (type, regcache, readbuf, regnum);
+
+ if (writebuf)
+ riscv_store_return_value (type, regcache, writebuf, regnum);
+
+ return RETURN_VALUE_REGISTER_CONVENTION;
+}
+
+static enum register_status
+riscv_pseudo_register_read (struct gdbarch *gdbarch,
+ struct regcache *regcache,
+ int regnum,
+ gdb_byte *buf)
+{
+ return regcache_raw_read (regcache, regnum, buf);
+}
+
+static void
+riscv_pseudo_register_write (struct gdbarch *gdbarch,
+ struct regcache *regcache,
+ int cookednum,
+ const gdb_byte *buf)
+{
+ regcache_raw_write (regcache, cookednum, buf);
+}
+
+static struct type *
+riscv_register_type (struct gdbarch *gdbarch,
+ int regnum)
+{
+ int regsize = riscv_isa_regsize (gdbarch);
+
+ if (regnum < RISCV_FIRST_FP_REGNUM)
+ {
+ int_regsizes:
+ switch (regsize)
+ {
+ case 4:
+ return builtin_type (gdbarch)->builtin_int32;
+ case 8:
+ return builtin_type (gdbarch)->builtin_int64;
+ case 16:
+ return builtin_type (gdbarch)->builtin_int128;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("unknown isa regsize %i"), regsize);
+ }
+ }
+ else if (regnum <= RISCV_LAST_FP_REGNUM)
+ {
+ switch (regsize)
+ {
+ case 4:
+ return builtin_type (gdbarch)->builtin_float;
+ case 8:
+ case 16:
+ return builtin_type (gdbarch)->builtin_double;
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("unknown isa regsize %i"), regsize);
+ }
+ }
+ else if (regnum == RISCV_PRIV_REGNUM)
+ {
+ return builtin_type (gdbarch)->builtin_int8;
+ }
+ else
+ {
+ if (regnum == RISCV_CSR_FFLAGS_REGNUM
+ || regnum == RISCV_CSR_FRM_REGNUM
+ || regnum == RISCV_CSR_FCSR_REGNUM)
+ return builtin_type (gdbarch)->builtin_int32;
+
+ goto int_regsizes;
+ }
+}
+
+/* TODO: Replace all this with tdesc XML files. */
+static void
+riscv_read_fp_register_single (struct frame_info *frame, int regno,
+ gdb_byte *rare_buffer)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ int raw_size = register_size (gdbarch, regno);
+ gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size);
+
+ if (!deprecated_frame_register_read (frame, regno, raw_buffer))
+ error (_("can't read register %d (%s)"), regno,
+ gdbarch_register_name (gdbarch, regno));
+
+ if (raw_size == 8)
+ {
+ int offset;
+
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ offset = 4;
+ else
+ offset = 0;
+
+ memcpy (rare_buffer, raw_buffer + offset, 4);
+ }
+ else
+ memcpy (rare_buffer, raw_buffer, 4);
+}
+
+static void
+riscv_read_fp_register_double (struct frame_info *frame, int regno,
+ gdb_byte *rare_buffer)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ int raw_size = register_size (gdbarch, regno);
+
+ if (raw_size == 8)
+ {
+ if (!deprecated_frame_register_read (frame, regno, rare_buffer))
+ error (_("can't read register %d (%s)"), regno,
+ gdbarch_register_name (gdbarch, regno));
+ }
+ else
+ internal_error (__FILE__, __LINE__,
+ _("%s: size says 32-bits, read is 64-bits."), __func__);
+}
+
+static void
+riscv_print_fp_register (struct ui_file *file, struct frame_info *frame,
+ int regnum)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ gdb_byte *raw_buffer;
+ struct value_print_options opts;
+ double val;
+ int inv;
+ const char *regname;
+
+ raw_buffer = (gdb_byte *) alloca (2 * register_size (gdbarch, RISCV_FIRST_FP_REGNUM));
+
+ fprintf_filtered (file, "%-15s", gdbarch_register_name (gdbarch, regnum));
+
+ if (register_size (gdbarch, regnum) == 4)
+ {
+ riscv_read_fp_register_single (frame, regnum, raw_buffer);
+ val = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer,
+ &inv);
+
+ get_formatted_print_options (&opts, 'x');
+ print_scalar_formatted (raw_buffer,
+ builtin_type (gdbarch)->builtin_float,
+ &opts, 'w', file);
+
+ if (!inv)
+ fprintf_filtered (file, "\t%-17.9g", val);
+ }
+ else
+ {
+ riscv_read_fp_register_double (frame, regnum, raw_buffer);
+ val = unpack_double (builtin_type (gdbarch)->builtin_double, raw_buffer,
+ &inv);
+
+ get_formatted_print_options (&opts, 'x');
+ print_scalar_formatted (raw_buffer,
+ builtin_type (gdbarch)->builtin_double,
+ &opts, 'g', file);
+
+ if (!inv)
+ fprintf_filtered (file, "\t%-24.17g", val);
+ }
+
+ if (inv)
+ fprintf_filtered (file, "\t<invalid>");
+}
+
+static void
+riscv_print_register_formatted (struct ui_file *file, struct frame_info *frame,
+ int regnum)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+ gdb_byte raw_buffer[MAX_REGISTER_SIZE];
+ struct value_print_options opts;
+
+ if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
+ riscv_print_fp_register (file, frame, regnum);
+ else
+ {
+ /* Integer type. */
+ int offset, size;
+ unsigned long long d;
+
+ if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
+ {
+ fprintf_filtered (file, "%-15s[Invalid]\n",
+ register_name (gdbarch, regnum, 1));
+ return;
+ }
+
+ fprintf_filtered (file, "%-15s", register_name (gdbarch, regnum, 1));
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ offset = register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
+ else
+ offset = 0;
+
+ size = register_size (gdbarch, regnum);
+ get_formatted_print_options (&opts, 'x');
+ print_scalar_formatted (raw_buffer + offset,
+ register_type (gdbarch, regnum), &opts,
+ size == 8 ? 'g' : 'w', file);
+ fprintf_filtered (file, "\t");
+ if (size == 4 && riscv_isa_regsize (gdbarch) == 8)
+ fprintf_filtered (file, "\t");
+
+ if (regnum == RISCV_CSR_MSTATUS_REGNUM)
+ {
+ d = unpack_long (builtin_type (gdbarch)->builtin_int32, raw_buffer);
+ fprintf_filtered (file, "IP:%02X IM:%02X EA:%d VM:%d S64:%d U64:%d EF:%d PEI:%d EI:%d PS:%d S:%d",
+ (int)((d >> 24) & 0xFF),
+ (int)((d >> 16) & 0xFF),
+ (int)((d >> 8) & 0x1),
+ (int)((d >> 7) & 0x1),
+ (int)((d >> 6) & 0x1),
+ (int)((d >> 5) & 0x1),
+ (int)((d >> 4) & 0x1),
+ (int)((d >> 3) & 0x1),
+ (int)((d >> 2) & 0x1),
+ (int)((d >> 1) & 0x1),
+ (int)((d >> 0) & 0x1));
+ }
+ else if (regnum == RISCV_CSR_MISA_REGNUM)
+ {
+ int base;
+ if (size == 4) {
+ d = unpack_long (builtin_type (gdbarch)->builtin_uint32, raw_buffer);
+ base = d >> 30;
+ } else if (size == 8) {
+ d = unpack_long (builtin_type (gdbarch)->builtin_uint64, raw_buffer);
+ base = d >> 62;
+ } else {
+ internal_error (__FILE__, __LINE__, _("unknown size for misa"));
+ }
+ unsigned xlen = 16;
+ for (; base > 0; base--) {
+ xlen *= 2;
+ }
+ fprintf_filtered (file, "RV%d", xlen);
+
+ for (unsigned i = 0; i < 26; i++) {
+ if (d & (1<<i)) {
+ fprintf_filtered (file, "%c", 'A' + i);
+ }
+ }
+ }
+ else if (regnum == RISCV_CSR_FCSR_REGNUM
+ || regnum == RISCV_CSR_FFLAGS_REGNUM
+ || regnum == RISCV_CSR_FRM_REGNUM)
+ {
+ d = unpack_long (builtin_type (gdbarch)->builtin_int32, raw_buffer);
+
+ if (regnum != RISCV_CSR_FRM_REGNUM)
+ fprintf_filtered (file, "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d ",
+ (int)((d >> 5) & 0x7),
+ (int)((d >> 4) & 0x1),
+ (int)((d >> 3) & 0x1),
+ (int)((d >> 2) & 0x1),
+ (int)((d >> 1) & 0x1),
+ (int)((d >> 0) & 0x1));
+
+ if (regnum != RISCV_CSR_FFLAGS_REGNUM)
+ {
+ static const char * const sfrm[] = {
+ "RNE (round to nearest; ties to even)",
+ "RTZ (Round towards zero)",
+ "RDN (Round down towards -∞)",
+ "RUP (Round up towards +∞)",
+ "RMM (Round to nearest; tiest to max magnitude)",
+ "INVALID[5]",
+ "INVALID[6]",
+ "dynamic rounding mode",
+ };
+ int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) ? (d >> 5) : d) & 0x3;
+
+ fprintf_filtered (file, "FRM:%i [%s]", frm, sfrm[frm]);
+ }
+ }
+ else if (regnum == RISCV_PRIV_REGNUM)
+ {
+ uint8_t priv = raw_buffer[0];
+ if (priv >= 0 && priv < 4)
+ {
+ static const char * const sprv[] = {
+ "User/Application",
+ "Supervisor",
+ "Hypervisor",
+ "Machine"
+ };
+ fprintf_filtered (file, "prv:%d [%s]", priv, sprv[priv]);
+ }
+ else
+ {
+ fprintf_filtered (file, "prv:%d [INVALID]", priv);
+ }
+ }
+ else
+ {
+ get_formatted_print_options (&opts, 'd');
+ print_scalar_formatted (raw_buffer + offset,
+ register_type (gdbarch, regnum),
+ &opts, 0, file);
+ }
+ }
+ fprintf_filtered (file, "\n");
+}
+
+static int
+riscv_register_reggroup_p (struct gdbarch *gdbarch,
+ int regnum,
+ struct reggroup *reggroup)
+{
+ int float_p;
+ int raw_p;
+ unsigned int i;
+
+ /* Used by 'info registers' and 'info registers <groupname>'. */
+
+ if (gdbarch_register_name (gdbarch, regnum) == NULL
+ || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
+ return 0;
+
+ if (reggroup == all_reggroup) {
+ if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
+ return 1;
+ /* Only include CSRs that have aliases. */
+ for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) {
+ if (regnum == riscv_register_aliases[i].regnum)
+ return 1;
+ }
+ return 0;
+ } else if (reggroup == float_reggroup)
+ return (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
+ || (regnum == RISCV_CSR_FCSR_REGNUM
+ || regnum == RISCV_CSR_FFLAGS_REGNUM
+ || regnum == RISCV_CSR_FRM_REGNUM);
+ else if (reggroup == general_reggroup)
+ return regnum < RISCV_FIRST_FP_REGNUM;
+ else if (reggroup == restore_reggroup || reggroup == save_reggroup)
+ return regnum <= RISCV_LAST_FP_REGNUM;
+ else if (reggroup == system_reggroup) {
+ if (regnum == RISCV_PRIV_REGNUM)
+ return 1;
+ if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
+ return 0;
+ /* Only include CSRs that have aliases. */
+ for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) {
+ if (regnum == riscv_register_aliases[i].regnum)
+ return 1;
+ }
+ return 0;
+ } else if (reggroup == vector_reggroup)
+ return 0;
+ else
+ internal_error (__FILE__, __LINE__, _("unhandled reggroup"));
+}
+
+static void
+riscv_print_registers_info (struct gdbarch *gdbarch,
+ struct ui_file *file,
+ struct frame_info *frame,
+ int regnum,
+ int all)
+{
+ /* Use by 'info all-registers'. */
+ struct reggroup *reggroup;
+
+ if (regnum != -1)
+ {
+ /* Print one specified register. */
+ gdb_assert (regnum <= RISCV_LAST_REGNUM);
+ if (NULL == register_name (gdbarch, regnum, 1))
+ error (_("Not a valid register for the current processor type"));
+ riscv_print_register_formatted (file, frame, regnum);
+ return;
+ }
+
+ if (all)
+ reggroup = all_reggroup;
+ else
+ reggroup = general_reggroup;
+ for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
+ {
+ /* Zero never changes, so might as well hide by default. */
+ if (regnum == RISCV_ZERO_REGNUM && !all)
+ continue;
+ if (riscv_register_reggroup_p(gdbarch, regnum, reggroup))
+ riscv_print_register_formatted (file, frame, regnum);
+ }
+}
+
+static ULONGEST
+riscv_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ gdb_byte buf[8];
+ int instlen, status;
+
+ /* All insns are at least 16 bits. */
+ status = target_read_memory (addr, buf, 2);
+ if (status)
+ memory_error (TARGET_XFER_E_IO, addr);
+
+ /* If we need more, grab it now. */
+ instlen = riscv_insn_length (buf[0]);
+ if (instlen > sizeof (buf))
+ internal_error (__FILE__, __LINE__, _("%s: riscv_insn_length returned %i"),
+ __func__, instlen);
+ else if (instlen > 2)
+ {
+ status = target_read_memory (addr + 2, buf + 2, instlen - 2);
+ if (status)
+ memory_error (TARGET_XFER_E_IO, addr + 2);
+ }
+
+ return extract_unsigned_integer (buf, instlen, byte_order);
+}
+
+static void
+set_reg_offset (struct gdbarch *gdbarch, struct riscv_frame_cache *this_cache,
+ int regnum, CORE_ADDR offset)
+{
+ if (this_cache != NULL && this_cache->saved_regs[regnum].addr == -1)
+ this_cache->saved_regs[regnum].addr = offset;
+}
+
+static void
+reset_saved_regs (struct gdbarch *gdbarch, struct riscv_frame_cache *this_cache)
+{
+ const int num_regs = gdbarch_num_regs (gdbarch);
+ int i;
+
+ if (this_cache == NULL || this_cache->saved_regs == NULL)
+ return;
+
+ for (i = 0; i < num_regs; ++i)
+ this_cache->saved_regs[i].addr = -1;
+}
+
+static CORE_ADDR
+riscv_scan_prologue (struct gdbarch *gdbarch,
+ CORE_ADDR start_pc, CORE_ADDR limit_pc,
+ struct frame_info *this_frame,
+ struct riscv_frame_cache *this_cache)
+{
+ CORE_ADDR cur_pc;
+ CORE_ADDR frame_addr = 0;
+ CORE_ADDR sp;
+ long frame_offset;
+ int frame_reg = RISCV_SP_REGNUM;
+
+ CORE_ADDR end_prologue_addr = 0;
+ int seen_sp_adjust = 0;
+ int load_immediate_bytes = 0;
+
+ /* Can be called when there's no process, and hence when there's no THIS_FRAME. */
+ if (this_frame != NULL)
+ sp = get_frame_register_signed (this_frame, RISCV_SP_REGNUM);
+ else
+ sp = 0;
+
+ if (limit_pc > start_pc + 200)
+ limit_pc = start_pc + 200;
+
+ restart:
+
+ frame_offset = 0;
+ /* TODO: Handle compressed extensions. */
+ for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4)
+ {
+ unsigned long inst, opcode;
+ int reg, rs1, imm12, rs2, offset12, funct3;
+
+ /* Fetch the instruction. */
+ inst = (unsigned long) riscv_fetch_instruction (gdbarch, cur_pc);
+ opcode = inst & 0x7F;
+ reg = (inst >> 7) & 0x1F;
+ rs1 = (inst >> 15) & 0x1F;
+ imm12 = (inst >> 20) & 0xFFF;
+ rs2 = (inst >> 20) & 0x1F;
+ offset12 = (((inst >> 25) & 0x7F) << 5) + ((inst >> 7) & 0x1F);
+ funct3 = (inst >> 12) & 0x7;
+
+ /* Look for common stack adjustment insns. */
+ if ((opcode == 0x13 || opcode == 0x1B) && reg == RISCV_SP_REGNUM
+ && rs1 == RISCV_SP_REGNUM)
+ {
+ /* addi sp, sp, -i */
+ /* addiw sp, sp, -i */
+ if (imm12 & 0x800)
+ frame_offset += 0x1000 - imm12;
+ else
+ break;
+ seen_sp_adjust = 1;
+ }
+ else if (opcode == 0x23 && funct3 == 0x2 && rs1 == RISCV_SP_REGNUM)
+ {
+ /* sw reg, offset(sp) */
+ set_reg_offset (gdbarch, this_cache, rs1, sp + offset12);
+ }
+ else if (opcode == 0x23 && funct3 == 0x3 && rs1 == RISCV_SP_REGNUM)
+ {
+ /* sd reg, offset(sp) */
+ set_reg_offset (gdbarch, this_cache, rs1, sp + offset12);
+ }
+ else if (opcode == 0x13 && reg == RISCV_FP_REGNUM && rs1 == RISCV_SP_REGNUM)
+ {
+ /* addi s0, sp, size */
+ if ((long)imm12 != frame_offset)
+ frame_addr = sp + imm12;
+ }
+ else if (this_frame && frame_reg == RISCV_SP_REGNUM)
+ {
+ unsigned alloca_adjust;
+
+ frame_reg = RISCV_FP_REGNUM;
+ frame_addr = get_frame_register_signed (this_frame, RISCV_FP_REGNUM);
+
+ alloca_adjust = (unsigned)(frame_addr - (sp - imm12));
+ if (alloca_adjust > 0)
+ {
+ sp += alloca_adjust;
+ reset_saved_regs (gdbarch, this_cache);
+ goto restart;
+ }
+ }
+ else if ((opcode == 0x33 || opcode == 0x3B) && reg == RISCV_FP_REGNUM
+ && rs1 == RISCV_SP_REGNUM && rs2 == RISCV_ZERO_REGNUM)
+ {
+ /* add s0, sp, 0 */
+ /* addw s0, sp, 0 */
+ if (this_frame && frame_reg == RISCV_SP_REGNUM)
+ {
+ unsigned alloca_adjust;
+ frame_reg = RISCV_FP_REGNUM;
+ frame_addr = get_frame_register_signed (this_frame,
+ RISCV_FP_REGNUM);
+
+ alloca_adjust = (unsigned)(frame_addr - sp);
+ if (alloca_adjust > 0)
+ {
+ sp = frame_addr;
+ reset_saved_regs (gdbarch, this_cache);
+ goto restart;
+ }
+ }
+ }
+ else if (opcode == 0x23 && funct3 == 0x2 && rs1 == RISCV_FP_REGNUM)
+ {
+ /* sw reg, offset(s0) */
+ set_reg_offset (gdbarch, this_cache, rs1, frame_addr + offset12);
+ }
+ else if (reg == RISCV_GP_REGNUM
+ && (opcode == 0x17 || opcode == 0x37
+ || (opcode == 0x13 && rs1 == RISCV_GP_REGNUM)
+ || (opcode == 0x33 && (rs1 == RISCV_GP_REGNUM
+ || rs2 == RISCV_GP_REGNUM))))
+ {
+ /* auipc gp, n */
+ /* addi gp, gp, n */
+ /* add gp, gp, reg */
+ /* add gp, reg, gp */
+ /* lui gp, n */
+ /* These instructions are part of the prologue, but we don't need to
+ do anything special to handle them. */
+ }
+ else
+ {
+ if (end_prologue_addr == 0)
+ end_prologue_addr = cur_pc;
+ }
+ }
+
+ if (this_cache != NULL)
+ {
+ this_cache->base = get_frame_register_signed (this_frame, frame_reg)
+ + frame_offset;
+ this_cache->saved_regs[RISCV_PC_REGNUM] =
+ this_cache->saved_regs[RISCV_RA_REGNUM];
+ }
+
+ if (end_prologue_addr == 0)
+ end_prologue_addr = cur_pc;
+
+ if (load_immediate_bytes && !seen_sp_adjust)
+ end_prologue_addr -= load_immediate_bytes;
+
+ return end_prologue_addr;
+}
+
+static CORE_ADDR
+riscv_skip_prologue (struct gdbarch *gdbarch,
+ CORE_ADDR pc)
+{
+ CORE_ADDR limit_pc;
+ CORE_ADDR func_addr;
+
+ /* See if we can determine the end of the prologue via the symbol table.
+ If so, then return either PC, or the PC after the prologue, whichever
+ is greater. */
+ if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
+ {
+ CORE_ADDR post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
+ if (post_prologue_pc != 0)
+ return std::max (pc, post_prologue_pc);
+ }
+
+ /* Can't determine prologue from the symbol table, need to examine
+ instructions. */
+
+ /* Find an upper limit on the function prologue using the debug information.
+ If the debug information could not be used to provide that bound, then use
+ an arbitrary large number as the upper bound. */
+ limit_pc = skip_prologue_using_sal (gdbarch, pc);
+ if (limit_pc == 0)
+ limit_pc = pc + 100; /* MAGIC! */
+
+ return riscv_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL);
+}
+
+static CORE_ADDR
+riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
+ struct value **args, int nargs, struct type *value_type,
+ CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
+ struct regcache *regcache)
+{
+ *bp_addr = sp;
+ *real_pc = funaddr;
+
+ /* Keep the stack aligned. */
+ return sp - 16;
+}
+
+static CORE_ADDR
+riscv_push_dummy_call (struct gdbarch *gdbarch,
+ struct value *function,
+ struct regcache *regcache,
+ CORE_ADDR bp_addr,
+ int nargs,
+ struct value **args,
+ CORE_ADDR sp,
+ int struct_return,
+ CORE_ADDR struct_addr)
+{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ gdb_byte buf[4];
+ int i;
+ CORE_ADDR func_addr = find_function_addr (function, NULL);
+
+ /* Push excess arguments in reverse order. */
+
+ for (i = nargs; i >= 8; --i)
+ {
+ struct type *value_type = value_enclosing_type (args[i]);
+ int container_len = align_up (TYPE_LENGTH (value_type), 3);
+
+ sp -= container_len;
+ write_memory (sp, value_contents_writeable (args[i]), container_len);
+ }
+
+ /* Initialize argument registers. */
+
+ for (i = 0; i < nargs && i < 8; ++i)
+ {
+ struct type *value_type = value_enclosing_type (args[i]);
+ const gdb_byte *arg_bits = value_contents_all (args[i]);
+ int regnum = TYPE_CODE (value_type) == TYPE_CODE_FLT ?
+ RISCV_FA0_REGNUM : RISCV_A0_REGNUM;
+
+ regcache_cooked_write_unsigned
+ (regcache, regnum + i,
+ extract_unsigned_integer (arg_bits, tdep->register_size, byte_order));
+ }
+
+ /* Store struct value address. */
+
+ if (struct_return)
+ regcache_cooked_write_unsigned (regcache, RISCV_A0_REGNUM, struct_addr);
+
+ /* Set the dummy return value to bp_addr.
+ A dummy breakpoint will be setup to execute the call. */
+
+ regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
+
+ /* Finally, update the stack pointer. */
+
+ regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
+
+ return sp;
+}
+
+static CORE_ADDR
+riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ return align_down (addr, 16);
+}
+
+static CORE_ADDR
+riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
+}
+
+static CORE_ADDR
+riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+ return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
+}
+
+static struct frame_id
+riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
+{
+ return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
+ get_frame_pc (this_frame));
+}
+
+static struct trad_frame_cache *
+riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
+{
+ CORE_ADDR pc;
+ CORE_ADDR start_addr;
+ CORE_ADDR stack_addr;
+ struct trad_frame_cache *this_trad_cache;
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+
+ if ((*this_cache) != NULL)
+ return (struct trad_frame_cache *) *this_cache;
+ this_trad_cache = trad_frame_cache_zalloc (this_frame);
+ (*this_cache) = this_trad_cache;
+
+ trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch),
+ RISCV_RA_REGNUM);
+
+ pc = get_frame_pc (this_frame);
+ find_pc_partial_function (pc, NULL, &start_addr, NULL);
+ stack_addr = get_frame_register_signed (this_frame, RISCV_SP_REGNUM);
+ trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
+
+ trad_frame_set_this_base (this_trad_cache, stack_addr);
+
+ return this_trad_cache;
+}
+
+static void
+riscv_frame_this_id (struct frame_info *this_frame,
+ void **prologue_cache,
+ struct frame_id *this_id)
+{
+ struct trad_frame_cache *info = riscv_frame_cache (this_frame, prologue_cache);
+ trad_frame_get_id (info, this_id);
+}
+
+static struct value *
+riscv_frame_prev_register (struct frame_info *this_frame,
+ void **prologue_cache,
+ int regnum)
+{
+ struct trad_frame_cache *info = riscv_frame_cache (this_frame, prologue_cache);
+ return trad_frame_get_register (info, this_frame, regnum);
+}
+
+static const struct frame_unwind riscv_frame_unwind =
+{
+ /*.type =*/ NORMAL_FRAME,
+ /*.stop_reason =*/ default_frame_unwind_stop_reason,
+ /*.this_id =*/ riscv_frame_this_id,
+ /*.prev_register =*/ riscv_frame_prev_register,
+ /*.unwind_data =*/ NULL,
+ /*.sniffer =*/ default_frame_sniffer,
+ /*.dealloc_cache =*/ NULL,
+ /*.prev_arch =*/ NULL,
+};
+
+static struct gdbarch *
+riscv_gdbarch_init (struct gdbarch_info info,
+ struct gdbarch_list *arches)
+{
+ struct gdbarch *gdbarch;
+ struct gdbarch_tdep *tdep;
+ const struct bfd_arch_info *binfo = info.bfd_arch_info;
+
+ int abi, i;
+
+ /* For now, base the abi on the elf class. */
+ /* Allow the ELF class to override the register size. Ideally the target
+ * (OpenOCD/spike/...) would communicate the register size to gdb instead. */
+ abi = RISCV_ABI_FLAG_RV32I;
+ if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
+ {
+ unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
+
+ if (eclass == ELFCLASS32)
+ abi = RISCV_ABI_FLAG_RV32I;
+ else if (eclass == ELFCLASS64)
+ abi = RISCV_ABI_FLAG_RV64I;
+ else
+ internal_error (__FILE__, __LINE__, _("unknown ELF header class %d"), eclass);
+ }
+ else
+ {
+ if (binfo->bits_per_word == 32)
+ abi = RISCV_ABI_FLAG_RV32I;
+ else if (binfo->bits_per_word == 64)
+ abi = RISCV_ABI_FLAG_RV64I;
+ else
+ internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
+ binfo->bits_per_word);
+ }
+
+ /* Find a candidate among the list of pre-declared architectures. */
+ for (arches = gdbarch_list_lookup_by_info (arches, &info);
+ arches != NULL;
+ arches = gdbarch_list_lookup_by_info (arches->next, &info))
+ if (gdbarch_tdep (arches->gdbarch)->riscv_abi == abi)
+ return arches->gdbarch;
+
+ /* None found, so create a new architecture from the information provided.
+ Can't initialize all the target dependencies until we actually know which
+ target we are talking to, but put in some defaults for now. */
+
+ tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
+ gdbarch = gdbarch_alloc (&info, tdep);
+
+ tdep->riscv_abi = abi;
+ switch (abi)
+ {
+ case RISCV_ABI_FLAG_RV32I:
+ tdep->register_size = 4;
+ break;
+ case RISCV_ABI_FLAG_RV64I:
+ tdep->register_size = 8;
+ break;
+ default:
+ internal_error (__FILE__, __LINE__, _("unknown abi %i"), abi);
+ tdep->register_size = 4;
+ break;
+ }
+
+ /* Target data types. */
+ set_gdbarch_short_bit (gdbarch, 16);
+ set_gdbarch_int_bit (gdbarch, 32);
+ set_gdbarch_long_bit (gdbarch, tdep->register_size * 8);
+ set_gdbarch_float_bit (gdbarch, 32);
+ set_gdbarch_double_bit (gdbarch, 64);
+ set_gdbarch_long_double_bit (gdbarch, 128);
+ set_gdbarch_ptr_bit (gdbarch, tdep->register_size * 8);
+ set_gdbarch_char_signed (gdbarch, 1);
+
+ /* Information about the target architecture. */
+ set_gdbarch_return_value (gdbarch, riscv_return_value);
+ set_gdbarch_breakpoint_from_pc (gdbarch, riscv_breakpoint_from_pc);
+ set_gdbarch_decr_pc_after_break (gdbarch, 4);
+ set_gdbarch_remote_breakpoint_from_pc (gdbarch, riscv_remote_breakpoint_from_pc);
+ set_gdbarch_print_insn (gdbarch, print_insn_riscv);
+
+ /* Register architecture. */
+ set_gdbarch_pseudo_register_read (gdbarch, riscv_pseudo_register_read);
+ set_gdbarch_pseudo_register_write (gdbarch, riscv_pseudo_register_write);
+ set_gdbarch_num_regs (gdbarch, RISCV_NUM_REGS);
+ set_gdbarch_num_pseudo_regs (gdbarch, RISCV_NUM_REGS);
+ set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
+ set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
+ set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
+ set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
+
+ /* Functions to supply register information. */
+ set_gdbarch_register_name (gdbarch, riscv_register_name);
+ set_gdbarch_register_type (gdbarch, riscv_register_type);
+ set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
+ set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
+
+ /* Functions to analyze frames. */
+ set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
+ set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+ set_gdbarch_frame_align (gdbarch, riscv_frame_align);
+
+ /* Functions to access frame data. */
+ set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
+ set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
+
+ /* Functions handling dummy frames. */
+ set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
+ set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
+ set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
+ set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
+
+ /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
+ unwinder. */
+ dwarf2_append_unwinders (gdbarch);
+ frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
+
+ /* Check any target description for validity. */
+ if (tdesc_has_registers (info.target_desc))
+ {
+ const struct tdesc_feature *feature;
+ struct tdesc_arch_data *tdesc_data;
+ int valid_p;
+
+ feature = tdesc_find_feature (info.target_desc, "org.gnu.gdb.riscv.cpu");
+ if (feature == NULL)
+ goto no_tdata;
+
+ tdesc_data = tdesc_data_alloc ();
+
+ valid_p = 1;
+ for (i = RISCV_ZERO_REGNUM; i <= RISCV_LAST_FP_REGNUM; ++i)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+ riscv_gdb_reg_names[i]);
+ for (i = RISCV_FIRST_CSR_REGNUM; i <= RISCV_LAST_CSR_REGNUM; ++i)
+ {
+ char buf[20];
+ sprintf (buf, "csr%d", i - RISCV_FIRST_CSR_REGNUM);
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i, buf);
+ }
+
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "priv");
+
+ if (!valid_p)
+ tdesc_data_cleanup (tdesc_data);
+ else
+ tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
+ }
+ no_tdata:
+
+ for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
+ user_reg_add (gdbarch, riscv_register_aliases[i].name,
+ value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
+
+ return gdbarch;
+}
+
+extern initialize_file_ftype _initialize_riscv_tdep; /* -Wmissing-prototypes */
+
+void
+_initialize_riscv_tdep (void)
+{
+ gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
+}
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
new file mode 100644
index 0000000..ef10209
--- /dev/null
+++ b/gdb/riscv-tdep.h
@@ -0,0 +1,101 @@
+/* Target-dependent header for the RISC-V architecture, for GDB, the GNU Debugger.
+
+ Copyright (C) 2002-2015 Free Software Foundation, Inc.
+
+ Contributed by Alessandro Forin(***@cs.cmu.edu) at CMU
+ and by Per Bothner(***@cs.wisc.edu) at U.Wisconsin
+ and by Todd Snyder <***@bluespec.com>
+ and by Mike Frysinger <***@gentoo.org>.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef RISCV_TDEP_H
+#define RISCV_TDEP_H
+
+struct gdbarch;
+
+/* All the official RISC-V ABIs. These mostly line up with mcpuid purely for
+ convenience. */
+#define RISCV_ABI_FLAG_RV32I (0x00000000) /* 32-bit Integer GPRs. */
+#define RISCV_ABI_FLAG_RV32E (0x10000000) /* 32-bit Embedded Integer GPRs. */
+#define RISCV_ABI_FLAG_RV64I (0x40000000) /* 64-bit Integer GPRs. */
+#define RISCV_ABI_FLAG_RV128I (0x80000000) /* 128-bit Integer GPRs. */
+#define RISCV_ABI_FLAG_A (1 << 0) /* Atomics. */
+#define RISCV_ABI_FLAG_B (1 << 1) /* Bit Manipulation. */
+#define RISCV_ABI_FLAG_C (1 << 2) /* 16-bit Compressed Instructions. */
+#define RISCV_ABI_FLAG_D (1 << 3) /* Double-Precision Floating-Point. */
+#define RISCV_ABI_FLAG_E (1 << 4) /* Embedded base. */
+#define RISCV_ABI_FLAG_F (1 << 5) /* Single-Precision Floating-Point. */
+#define RISCV_ABI_FLAG_H (1 << 7) /* Hypervisor mode. */
+#define RISCV_ABI_FLAG_I (1 << 8) /* Base integer. */
+#define RISCV_ABI_FLAG_L (1 << 11) /* Decimal Floating-Point. */
+#define RISCV_ABI_FLAG_M (1 << 12) /* Integer Multiply and Division. */
+#define RISCV_ABI_FLAG_P (1 << 15) /* Packed-SIMD Extensions. */
+#define RISCV_ABI_FLAG_Q (1 << 16) /* Quad-Precision Floating-Point. */
+#define RISCV_ABI_FLAG_S (1 << 18) /* Supervisor mode. */
+#define RISCV_ABI_FLAG_T (1 << 19) /* Transactional Memory. */
+#define RISCV_ABI_FLAG_U (1 << 20) /* User mode. */
+
+#define IS_RV32I(x) (((x) & 0xF0000000) == RISCV_ABI_FLAG_RV32I)
+#define IS_RV64I(x) (((x) & 0xF0000000) == RISCV_ABI_FLAG_RV64I)
+#define IS_RV128I(x) (((x) & 0xF0000000) == RISCV_ABI_FLAG_RV128I)
+
+#define HAS_FPU(x) ((x) & (RISCV_ABI_FLAG_D | RISCV_ABI_FLAG_F))
+
+enum {
+ RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
+ RISCV_RA_REGNUM = 1, /* Return Address. */
+ RISCV_SP_REGNUM = 2, /* Stack Pointer. */
+ RISCV_GP_REGNUM = 3, /* Global Pointer. */
+ RISCV_TP_REGNUM = 4, /* Thread Pointer. */
+ RISCV_FP_REGNUM = 8, /* Frame Pointer. */
+ RISCV_A0_REGNUM = 10, /* First argument. */
+ RISCV_A1_REGNUM = 11, /* Second argument. */
+ RISCV_PC_REGNUM = 32, /* Program Counter. */
+
+ RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
+ RISCV_FA0_REGNUM = 49,
+ RISCV_FA1_REGNUM = 50,
+ RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
+
+ RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
+#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ RISCV_LAST_CSR_REGNUM = 4160,
+
+ RISCV_PRIV_REGNUM = 4161,
+
+ /* Leave this as the last enum. */
+ RISCV_NUM_REGS
+};
+
+#define RISCV_LAST_REGNUM (RISCV_NUM_REGS - 1)
+
+/* RISC-V specific per-architecture information. */
+struct gdbarch_tdep
+{
+ int riscv_abi;
+ int register_size;
+};
+
+static inline int
+riscv_isa_regsize (struct gdbarch *gdbarch)
+{
+ return gdbarch_tdep (gdbarch)->register_size;
+}
+
+#endif /* RISCV_TDEP_H */
diff --git a/include/gdb/sim-riscv.h b/include/gdb/sim-riscv.h
new file mode 100644
index 0000000..932cf49
--- /dev/null
+++ b/include/gdb/sim-riscv.h
@@ -0,0 +1,98 @@
+/* This file defines the interface between the RISC-V simulator and GDB.
+
+ Copyright (C) 2005-2015 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Order has to match gdb riscv-tdep list. */
+enum sim_riscv_regnum {
+ SIM_RISCV_ZERO_REGNUM = 0,
+ SIM_RISCV_RA_REGNUM,
+ SIM_RISCV_SP_REGNUM,
+ SIM_RISCV_GP_REGNUM,
+ SIM_RISCV_TP_REGNUM,
+ SIM_RISCV_T0_REGNUM,
+ SIM_RISCV_T1_REGNUM,
+ SIM_RISCV_T2_REGNUM,
+ SIM_RISCV_S0_REGNUM,
+#define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM
+ SIM_RISCV_S1_REGNUM,
+ SIM_RISCV_A0_REGNUM,
+ SIM_RISCV_A1_REGNUM,
+ SIM_RISCV_A2_REGNUM,
+ SIM_RISCV_A3_REGNUM,
+ SIM_RISCV_A4_REGNUM,
+ SIM_RISCV_A5_REGNUM,
+ SIM_RISCV_A6_REGNUM,
+ SIM_RISCV_A7_REGNUM,
+ SIM_RISCV_S2_REGNUM,
+ SIM_RISCV_S3_REGNUM,
+ SIM_RISCV_S4_REGNUM,
+ SIM_RISCV_S5_REGNUM,
+ SIM_RISCV_S6_REGNUM,
+ SIM_RISCV_S7_REGNUM,
+ SIM_RISCV_S8_REGNUM,
+ SIM_RISCV_S9_REGNUM,
+ SIM_RISCV_S10_REGNUM,
+ SIM_RISCV_S11_REGNUM,
+ SIM_RISCV_T3_REGNUM,
+ SIM_RISCV_T4_REGNUM,
+ SIM_RISCV_T5_REGNUM,
+ SIM_RISCV_T6_REGNUM,
+ SIM_RISCV_PC_REGNUM,
+ SIM_RISCV_FT0_REGNUM,
+#define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM
+ SIM_RISCV_FT1_REGNUM,
+ SIM_RISCV_FT2_REGNUM,
+ SIM_RISCV_FT3_REGNUM,
+ SIM_RISCV_FT4_REGNUM,
+ SIM_RISCV_FT5_REGNUM,
+ SIM_RISCV_FT6_REGNUM,
+ SIM_RISCV_FT7_REGNUM,
+ SIM_RISCV_FS0_REGNUM,
+ SIM_RISCV_FS1_REGNUM,
+ SIM_RISCV_FA0_REGNUM,
+ SIM_RISCV_FA1_REGNUM,
+ SIM_RISCV_FA2_REGNUM,
+ SIM_RISCV_FA3_REGNUM,
+ SIM_RISCV_FA4_REGNUM,
+ SIM_RISCV_FA5_REGNUM,
+ SIM_RISCV_FA6_REGNUM,
+ SIM_RISCV_FA7_REGNUM,
+ SIM_RISCV_FS2_REGNUM,
+ SIM_RISCV_FS3_REGNUM,
+ SIM_RISCV_FS4_REGNUM,
+ SIM_RISCV_FS5_REGNUM,
+ SIM_RISCV_FS6_REGNUM,
+ SIM_RISCV_FS7_REGNUM,
+ SIM_RISCV_FS8_REGNUM,
+ SIM_RISCV_FS9_REGNUM,
+ SIM_RISCV_FS10_REGNUM,
+ SIM_RISCV_FS11_REGNUM,
+ SIM_RISCV_FT8_REGNUM,
+ SIM_RISCV_FT9_REGNUM,
+ SIM_RISCV_FT10_REGNUM,
+ SIM_RISCV_FT11_REGNUM,
+#define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM
+
+#define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1
+#define DECLARE_CSR(name, num) SIM_RISCV_ ## num ## _REGNUM,
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+#define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1
+
+ SIM_RISCV_LAST_REGNUM
+};
--
2.7.3
Alan Modra
2016-10-12 01:01:32 UTC
Permalink
The gdb and sim parts should be posted to gdb-***@sourceware.org,
compressing and attaching the sim part since it seems to be too big
for the mailing list.
--
Alan Modra
Australia Development Lab, IBM
Andrew Waterman
2016-10-11 23:46:10 UTC
Permalink
---
ld/emulparams/elf32lriscv-defs.sh | 42 ++++++++++++++++++++++++
ld/emulparams/elf32lriscv.sh | 2 ++
ld/emulparams/elf64lriscv-defs.sh | 13 ++++++++
ld/emulparams/elf64lriscv.sh | 2 ++
ld/emultempl/riscvelf.em | 68 +++++++++++++++++++++++++++++++++++++++
5 files changed, 127 insertions(+)
create mode 100644 ld/emulparams/elf32lriscv-defs.sh
create mode 100644 ld/emulparams/elf32lriscv.sh
create mode 100644 ld/emulparams/elf64lriscv-defs.sh
create mode 100644 ld/emulparams/elf64lriscv.sh
create mode 100644 ld/emultempl/riscvelf.em

diff --git a/ld/emulparams/elf32lriscv-defs.sh b/ld/emulparams/elf32lriscv-defs.sh
new file mode 100644
index 0000000..0e4b723
--- /dev/null
+++ b/ld/emulparams/elf32lriscv-defs.sh
@@ -0,0 +1,42 @@
+# This is an ELF platform.
+SCRIPT_NAME=elf
+ARCH=riscv
+NO_REL_RELOCS=yes
+
+TEMPLATE_NAME=elf32
+EXTRA_EM_FILE=riscvelf
+
+ELFSIZE=32
+
+if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then
+ case " $EMULATION_LIBPATH " in
+ *" ${EMULATION_NAME} "*)
+ NATIVE=yes
+ ;;
+ esac
+fi
+
+GENERATE_SHLIB_SCRIPT=yes
+GENERATE_PIE_SCRIPT=yes
+
+TEXT_START_ADDR=0x10000
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
+
+SDATA_START_SYMBOLS="_gp = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)"
+
+# Place the data section before text section. This enables more compact
+# global variable access for RVC code via linker relaxation.
+INITIAL_READONLY_SECTIONS="
+ .data : { *(.data) *(.data.*) *(.gnu.linkonce.d.*) }
+ .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) }
+ .srodata : { ${SDATA_START_SYMBOLS} }
+ .sdata : { *(.sdata .sdata.* .gnu.linkonce.s.*) }
+ .sbss : { *(.dynsbss) *(.sbss .sbss.* .gnu.linkonce.sb.*) }
+ .bss : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }
+ . = ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1));"
+INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}"
+INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}"
+
+SDATA_START_SYMBOLS="${CREATE_PIE+${SDATA_START_SYMBOLS}}"
diff --git a/ld/emulparams/elf32lriscv.sh b/ld/emulparams/elf32lriscv.sh
new file mode 100644
index 0000000..aac08e7
--- /dev/null
+++ b/ld/emulparams/elf32lriscv.sh
@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/elf32lriscv-defs.sh
+OUTPUT_FORMAT="elf32-littleriscv"
diff --git a/ld/emulparams/elf64lriscv-defs.sh b/ld/emulparams/elf64lriscv-defs.sh
new file mode 100644
index 0000000..6308714
--- /dev/null
+++ b/ld/emulparams/elf64lriscv-defs.sh
@@ -0,0 +1,13 @@
+. ${srcdir}/emulparams/elf32lriscv-defs.sh
+ELFSIZE=64
+
+# Look for 64 bit target libraries in /lib64, /usr/lib64 etc., first
+# on Linux.
+case "$target" in
+ riscv64*-linux*)
+ case "$EMULATION_NAME" in
+ *64*)
+ LIBPATH_SUFFIX=64 ;;
+ esac
+ ;;
+esac
diff --git a/ld/emulparams/elf64lriscv.sh b/ld/emulparams/elf64lriscv.sh
new file mode 100644
index 0000000..3a6a652
--- /dev/null
+++ b/ld/emulparams/elf64lriscv.sh
@@ -0,0 +1,2 @@
+. ${srcdir}/emulparams/elf64lriscv-defs.sh
+OUTPUT_FORMAT="elf64-littleriscv"
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
new file mode 100644
index 0000000..de35cc1
--- /dev/null
+++ b/ld/emultempl/riscvelf.em
@@ -0,0 +1,68 @@
+# This shell script emits a C file. -*- C -*-
+# Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+fragment <<EOF
+
+#include "ldmain.h"
+#include "ldctor.h"
+#include "elf/riscv.h"
+#include "elfxx-riscv.h"
+
+static void
+riscv_elf_before_allocation (void)
+{
+ gld${EMULATION_NAME}_before_allocation ();
+
+ if (link_info.discard == discard_sec_merge)
+ link_info.discard = discard_l;
+
+ /* We always need at least some relaxation to handle code alignment. */
+ if (RELAXATION_DISABLED_BY_USER)
+ TARGET_ENABLE_RELAXATION;
+ else
+ ENABLE_RELAXATION;
+
+ link_info.relax_pass = 2;
+}
+
+static void
+gld${EMULATION_NAME}_after_allocation (void)
+{
+ int need_layout = 0;
+
+ /* Don't attempt to discard unused .eh_frame sections until the final link,
+ as we can't reliably tell if they're used until after relaxation. */
+ if (!bfd_link_relocatable (&link_info))
+ {
+ need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+ if (need_layout < 0)
+ {
+ einfo ("%X%P: .eh_frame/.stab edit: %E\n");
+ return;
+ }
+ }
+
+ gld${EMULATION_NAME}_map_segments (need_layout);
+}
+
+EOF
+
+LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation
+LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
--
2.7.3
Nick Clifton
2016-10-14 14:43:49 UTC
Permalink
Hi Andrew,
Post by Andrew Waterman
+++ b/ld/emultempl/riscvelf.em
@@ -0,0 +1,68 @@
+# This shell script emits a C file. -*- C -*-
+# Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
Please update the copyright date and add a ld/NEWS entry.
Otherwise looking good.

Cheers
Nick
Andrew Waterman
2016-10-11 23:46:07 UTC
Permalink
This post might be inappropriate. Click to display it.
Nick Clifton
2016-10-14 14:12:00 UTC
Permalink
Hi Andrew,

As an aside I would like to point out that it would be helpful if you
could include proposed ChangeLog entries for each of these patches.

Also with a new target like this, an entry in the gas/NEWS file is
appropriate. Plus I notice that your patch does not add a new
gas/doc/c-riscv.texi file, nor does it update gas/doc/as.texinfo,
and it does not appear to contain a new sub-directory in
gas/testsuite/gas for RISC-V specific tests. All of these would
really be appreciated.
Post by Andrew Waterman
+/* tc-riscv.c -- RISC-V assembler
+ Copyright 2011-2015 Free Software Foundation, Inc.
Given that this file is only being contributed in 2016, it is difficult
to see how the FSF can claim copyright for 2011..2015. :-) (The same
thing applies to the other new files too...)
Post by Andrew Waterman
+riscv_set_arch (const char *arg)
+{
+ char *uppercase = xstrdup (arg);
+ char *p = uppercase;
+ const char *all_subsets = "IMAFDC";
+ const char *extension = NULL;
+ int rvc = 0;
+ int i;
+
+ for (i = 0; uppercase[i]; i++)
+ uppercase[i] = TOUPPER (uppercase[i]);
You could save code space and memory allocation by using strncasecmp
instead if strncmp...
Post by Andrew Waterman
+/* handle of the OPCODE hash table */
Comment formatting - upper case first letter, period and two spaces at
the end.
Post by Andrew Waterman
+static int
+relaxed_branch_length (fragS *fragp, asection *sec, int update)
Can a relaxed branch ever have a negative length ? If not then "unsigned int"
would be a more appropriate return type.
Post by Andrew Waterman
+static int
+arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
Similarly this appears to be a boolean function so bfd_boolean would be a more
appropriate return type. (Actually there appear to be quite a few functions that
should be returning a boolean).
Post by Andrew Waterman
+append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
+ bfd_reloc_code_real_type reloc_type)
+{
+#ifdef OBJ_ELF
+ dwarf2_emit_insn (0);
+#endif
Are you supporting file formats other than ELF ? If not, then there
is no need for the conditionals around this code.
Post by Andrew Waterman
+ switch (elf_float_mode)
+ {
+ as_bad ("a specific float mode must be specified for an ELF");
+ break;
This error message looks a little wrong to me. I think that
dropping the "for an ELF" part would make more sense.
Post by Andrew Waterman
+void
+md_show_usage (FILE *stream)
+{
+ fprintf (stream, _("\
+RISC-V options:\n\
+ -m32 assemble RV32 code\n\
+ -m64 assemble RV64 code (default)\n\
+ -fpic generate position-independent code\n\
+ -fno-pic don't generate position-independent code (default)\n\
+"));
There are more command line options supported than those show here.
-march, -mrvc, -msoft-float and -mhard-float for example.

Cheers
Nick
Andrew Waterman
2016-10-11 23:46:06 UTC
Permalink
---
bfd/cpu-riscv.c | 79 ++
bfd/elfnn-riscv.c | 3142 +++++++++++++++++++++++++++++++++++++++++++++++++++
bfd/elfxx-riscv.c | 814 +++++++++++++
bfd/elfxx-riscv.h | 33 +
include/elf/riscv.h | 92 ++
5 files changed, 4160 insertions(+)
create mode 100644 bfd/cpu-riscv.c
create mode 100644 bfd/elfnn-riscv.c
create mode 100644 bfd/elfxx-riscv.c
create mode 100644 bfd/elfxx-riscv.h
create mode 100644 include/elf/riscv.h

diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
new file mode 100644
index 0000000..0a1c0e6
--- /dev/null
+++ b/bfd/cpu-riscv.c
@@ -0,0 +1,79 @@
+/* BFD backend for RISC-V
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on MIPS target.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+/* This routine is provided two arch_infos and returns an arch_info
+ that is compatible with both, or NULL if none exists. */
+
+static const bfd_arch_info_type *
+riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
+{
+ if (a->arch != b->arch)
+ return NULL;
+
+ /* Machine compatibility is checked in
+ _bfd_riscv_elf_merge_private_bfd_data. */
+
+ return a;
+}
+
+#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
+ { \
+ BITS_WORD, /* bits in a word */ \
+ BITS_ADDR, /* bits in an address */ \
+ 8, /* 8 bits in a byte */ \
+ bfd_arch_riscv, \
+ NUMBER, \
+ "riscv", \
+ PRINT, \
+ 3, \
+ DEFAULT, \
+ riscv_compatible, \
+ bfd_default_scan, \
+ bfd_arch_default_fill, \
+ NEXT, \
+ }
+
+/* This enum must be kept in the same order as arch_info_struct. */
+enum
+{
+ I_riscv64,
+ I_riscv32
+};
+
+#define NN(index) (&arch_info_struct[(index) + 1])
+
+/* This array must be kept in the same order as the anonymous enum above,
+ and each entry except the last should end with NN (my enum value). */
+static const bfd_arch_info_type arch_info_struct[] =
+{
+ N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)),
+ N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0)
+};
+
+/* The default architecture is riscv:rv64. */
+
+const bfd_arch_info_type bfd_riscv_arch =
+ N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
new file mode 100644
index 0000000..47baa93
--- /dev/null
+++ b/bfd/elfnn-riscv.c
@@ -0,0 +1,3142 @@
+/* RISC-V-specific support for NN-bit ELF.
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on TILE-Gx and MIPS targets.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* This file handles RISC-V ELF targets. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "bfdlink.h"
+#include "genlink.h"
+#include "elf-bfd.h"
+#include "elfxx-riscv.h"
+#include "elf/riscv.h"
+#include "opcode/riscv.h"
+
+#define ARCH_SIZE NN
+
+#define MINUS_ONE ((bfd_vma)0 - 1)
+
+#define RISCV_ELF_LOG_WORD_BYTES (ARCH_SIZE == 32 ? 2 : 3)
+
+#define RISCV_ELF_WORD_BYTES (1 << RISCV_ELF_LOG_WORD_BYTES)
+
+/* The name of the dynamic interpreter. This is put in the .interp
+ section. */
+
+#define ELF64_DYNAMIC_INTERPRETER "/lib/ld.so.1"
+#define ELF32_DYNAMIC_INTERPRETER "/lib32/ld.so.1"
+
+#define ELF_ARCH bfd_arch_riscv
+#define ELF_TARGET_ID RISCV_ELF_DATA
+#define ELF_MACHINE_CODE EM_RISCV
+#define ELF_MAXPAGESIZE 0x1000
+#define ELF_COMMONPAGESIZE 0x1000
+
+/* The RISC-V linker needs to keep track of the number of relocs that it
+ decides to copy as dynamic relocs in check_relocs for each symbol.
+ This is so that it can later discard them if they are found to be
+ unnecessary. We store the information in a field extending the
+ regular ELF linker hash table. */
+
+struct riscv_elf_dyn_relocs
+{
+ struct riscv_elf_dyn_relocs *next;
+
+ /* The input section of the reloc. */
+ asection *sec;
+
+ /* Total number of relocs copied for the input section. */
+ bfd_size_type count;
+
+ /* Number of pc-relative relocs copied for the input section. */
+ bfd_size_type pc_count;
+};
+
+/* RISC-V ELF linker hash entry. */
+
+struct riscv_elf_link_hash_entry
+{
+ struct elf_link_hash_entry elf;
+
+ /* Track dynamic relocs copied for this symbol. */
+ struct riscv_elf_dyn_relocs *dyn_relocs;
+
+#define GOT_UNKNOWN 0
+#define GOT_NORMAL 1
+#define GOT_TLS_GD 2
+#define GOT_TLS_IE 4
+#define GOT_TLS_LE 8
+ char tls_type;
+};
+
+#define riscv_elf_hash_entry(ent) \
+ ((struct riscv_elf_link_hash_entry *)(ent))
+
+struct _bfd_riscv_elf_obj_tdata
+{
+ struct elf_obj_tdata root;
+
+ /* tls_type for each local got entry. */
+ char *local_got_tls_type;
+};
+
+#define _bfd_riscv_elf_tdata(abfd) \
+ ((struct _bfd_riscv_elf_obj_tdata *) (abfd)->tdata.any)
+
+#define _bfd_riscv_elf_local_got_tls_type(abfd) \
+ (_bfd_riscv_elf_tdata (abfd)->local_got_tls_type)
+
+#define _bfd_riscv_elf_tls_type(abfd, h, symndx) \
+ (*((h) != NULL ? &riscv_elf_hash_entry (h)->tls_type \
+ : &_bfd_riscv_elf_local_got_tls_type (abfd) [symndx]))
+
+#define is_riscv_elf(bfd) \
+ (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
+ && elf_tdata (bfd) != NULL \
+ && elf_object_id (bfd) == RISCV_ELF_DATA)
+
+#include "elf/common.h"
+#include "elf/internal.h"
+
+struct riscv_elf_link_hash_table
+{
+ struct elf_link_hash_table elf;
+
+ /* Short-cuts to get to dynamic linker sections. */
+ asection *sdynbss;
+ asection *srelbss;
+ asection *sdyntdata;
+
+ /* Small local sym to section mapping cache. */
+ struct sym_cache sym_cache;
+};
+
+
+/* Get the RISC-V ELF linker hash table from a link_info structure. */
+#define riscv_elf_hash_table(p) \
+ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
+ == RISCV_ELF_DATA ? ((struct riscv_elf_link_hash_table *) ((p)->hash)) : NULL)
+
+static void
+riscv_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *cache_ptr,
+ Elf_Internal_Rela *dst)
+{
+ cache_ptr->howto = riscv_elf_rtype_to_howto (ELFNN_R_TYPE (dst->r_info));
+}
+
+static void
+riscv_elf_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel)
+{
+ const struct elf_backend_data *bed;
+ bfd_byte *loc;
+
+ bed = get_elf_backend_data (abfd);
+ loc = s->contents + (s->reloc_count++ * bed->s->sizeof_rela);
+ bed->s->swap_reloca_out (abfd, rel, loc);
+}
+
+/* PLT/GOT stuff */
+
+#define PLT_HEADER_INSNS 8
+#define PLT_ENTRY_INSNS 4
+#define PLT_HEADER_SIZE (PLT_HEADER_INSNS * 4)
+#define PLT_ENTRY_SIZE (PLT_ENTRY_INSNS * 4)
+
+#define GOT_ENTRY_SIZE RISCV_ELF_WORD_BYTES
+
+#define GOTPLT_HEADER_SIZE (2 * GOT_ENTRY_SIZE)
+
+#define sec_addr(sec) ((sec)->output_section->vma + (sec)->output_offset)
+
+static bfd_vma
+riscv_elf_got_plt_val (bfd_vma plt_index, struct bfd_link_info *info)
+{
+ return sec_addr (riscv_elf_hash_table (info)->elf.sgotplt)
+ + GOTPLT_HEADER_SIZE + (plt_index * GOT_ENTRY_SIZE);
+}
+
+#if ARCH_SIZE == 32
+# define MATCH_LREG MATCH_LW
+#else
+# define MATCH_LREG MATCH_LD
+#endif
+
+/* Generate a PLT header. */
+
+static void
+riscv_make_plt_header (bfd_vma gotplt_addr, bfd_vma addr, uint32_t *entry)
+{
+ bfd_vma gotplt_offset_high = RISCV_PCREL_HIGH_PART (gotplt_addr, addr);
+ bfd_vma gotplt_offset_low = RISCV_PCREL_LOW_PART (gotplt_addr, addr);
+
+ /* auipc t2, %hi(.got.plt)
+ sub t1, t1, t3 # shifted .got.plt offset + hdr size + 12
+ l[w|d] t3, %lo(.got.plt)(t2) # _dl_runtime_resolve
+ addi t1, t1, -(hdr size + 12) # shifted .got.plt offset
+ addi t0, t2, %lo(.got.plt) # &.got.plt
+ srli t1, t1, log2(16/PTRSIZE) # .got.plt offset
+ l[w|d] t0, PTRSIZE(t0) # link map
+ jr t3 */
+
+ entry[0] = RISCV_UTYPE (AUIPC, X_T2, gotplt_offset_high);
+ entry[1] = RISCV_RTYPE (SUB, X_T1, X_T1, X_T3);
+ entry[2] = RISCV_ITYPE (LREG, X_T3, X_T2, gotplt_offset_low);
+ entry[3] = RISCV_ITYPE (ADDI, X_T1, X_T1, -(PLT_HEADER_SIZE + 12));
+ entry[4] = RISCV_ITYPE (ADDI, X_T0, X_T2, gotplt_offset_low);
+ entry[5] = RISCV_ITYPE (SRLI, X_T1, X_T1, 4 - RISCV_ELF_LOG_WORD_BYTES);
+ entry[6] = RISCV_ITYPE (LREG, X_T0, X_T0, RISCV_ELF_WORD_BYTES);
+ entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0);
+}
+
+/* Generate a PLT entry. */
+
+static void
+riscv_make_plt_entry (bfd_vma got, bfd_vma addr, uint32_t *entry)
+{
+ /* auipc t3, %hi(.got.plt entry)
+ l[w|d] t3, %lo(.got.plt entry)(t3)
+ jalr t1, t3
+ nop */
+
+ entry[0] = RISCV_UTYPE (AUIPC, X_T3, RISCV_PCREL_HIGH_PART (got, addr));
+ entry[1] = RISCV_ITYPE (LREG, X_T3, X_T3, RISCV_PCREL_LOW_PART(got, addr));
+ entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
+ entry[3] = RISCV_NOP;
+}
+
+/* Create an entry in an RISC-V ELF linker hash table. */
+
+static struct bfd_hash_entry *
+link_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table, const char *string)
+{
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (entry == NULL)
+ {
+ entry =
+ bfd_hash_allocate (table,
+ sizeof (struct riscv_elf_link_hash_entry));
+ if (entry == NULL)
+ return entry;
+ }
+
+ /* Call the allocation method of the superclass. */
+ entry = _bfd_elf_link_hash_newfunc (entry, table, string);
+ if (entry != NULL)
+ {
+ struct riscv_elf_link_hash_entry *eh;
+
+ eh = (struct riscv_elf_link_hash_entry *) entry;
+ eh->dyn_relocs = NULL;
+ eh->tls_type = GOT_UNKNOWN;
+ }
+
+ return entry;
+}
+
+/* Create a RISC-V ELF linker hash table. */
+
+static struct bfd_link_hash_table *
+riscv_elf_link_hash_table_create (bfd *abfd)
+{
+ struct riscv_elf_link_hash_table *ret;
+ bfd_size_type amt = sizeof (struct riscv_elf_link_hash_table);
+
+ ret = (struct riscv_elf_link_hash_table *) bfd_zmalloc (amt);
+ if (ret == NULL)
+ return NULL;
+
+ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
+ sizeof (struct riscv_elf_link_hash_entry),
+ RISCV_ELF_DATA))
+ {
+ free (ret);
+ return NULL;
+ }
+
+ return &ret->elf.root;
+}
+
+/* Create the .got section. */
+
+static bfd_boolean
+riscv_elf_create_got_section (bfd *abfd, struct bfd_link_info *info)
+{
+ flagword flags;
+ asection *s, *s_got;
+ struct elf_link_hash_entry *h;
+ const struct elf_backend_data *bed = get_elf_backend_data (abfd);
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+
+ /* This function may be called more than once. */
+ s = bfd_get_linker_section (abfd, ".got");
+ if (s != NULL)
+ return TRUE;
+
+ flags = bed->dynamic_sec_flags;
+
+ s = bfd_make_section_anyway_with_flags (abfd,
+ (bed->rela_plts_and_copies_p
+ ? ".rela.got" : ".rel.got"),
+ (bed->dynamic_sec_flags
+ | SEC_READONLY));
+ if (s == NULL
+ || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align))
+ return FALSE;
+ htab->srelgot = s;
+
+ s = s_got = bfd_make_section_anyway_with_flags (abfd, ".got", flags);
+ if (s == NULL
+ || !bfd_set_section_alignment (abfd, s, bed->s->log_file_align))
+ return FALSE;
+ htab->sgot = s;
+
+ /* The first bit of the global offset table is the header. */
+ s->size += bed->got_header_size;
+
+ if (bed->want_got_plt)
+ {
+ s = bfd_make_section_anyway_with_flags (abfd, ".got.plt", flags);
+ if (s == NULL
+ || !bfd_set_section_alignment (abfd, s,
+ bed->s->log_file_align))
+ return FALSE;
+ htab->sgotplt = s;
+
+ /* Reserve room for the header. */
+ s->size += GOTPLT_HEADER_SIZE;
+ }
+
+ if (bed->want_got_sym)
+ {
+ /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got
+ section. We don't do this in the linker script because we don't want
+ to define the symbol if we are not creating a global offset
+ table. */
+ h = _bfd_elf_define_linkage_sym (abfd, info, s_got,
+ "_GLOBAL_OFFSET_TABLE_");
+ elf_hash_table (info)->hgot = h;
+ if (h == NULL)
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/* Create .plt, .rela.plt, .got, .got.plt, .rela.got, .dynbss, and
+ .rela.bss sections in DYNOBJ, and set up shortcuts to them in our
+ hash table. */
+
+static bfd_boolean
+riscv_elf_create_dynamic_sections (bfd *dynobj,
+ struct bfd_link_info *info)
+{
+ struct riscv_elf_link_hash_table *htab;
+
+ htab = riscv_elf_hash_table (info);
+ BFD_ASSERT (htab != NULL);
+
+ if (!riscv_elf_create_got_section (dynobj, info))
+ return FALSE;
+
+ if (!_bfd_elf_create_dynamic_sections (dynobj, info))
+ return FALSE;
+
+ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
+ if (!bfd_link_pic (info))
+ {
+ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
+ htab->sdyntdata =
+ bfd_make_section_anyway_with_flags (dynobj, ".tdata.dyn",
+ SEC_ALLOC | SEC_THREAD_LOCAL);
+ }
+
+ if (!htab->elf.splt || !htab->elf.srelplt || !htab->sdynbss
+ || (!bfd_link_pic (info) && (!htab->srelbss || !htab->sdyntdata)))
+ abort ();
+
+ return TRUE;
+}
+
+/* Copy the extra info we tack onto an elf_link_hash_entry. */
+
+static void
+riscv_elf_copy_indirect_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *dir,
+ struct elf_link_hash_entry *ind)
+{
+ struct riscv_elf_link_hash_entry *edir, *eind;
+
+ edir = (struct riscv_elf_link_hash_entry *) dir;
+ eind = (struct riscv_elf_link_hash_entry *) ind;
+
+ if (eind->dyn_relocs != NULL)
+ {
+ if (edir->dyn_relocs != NULL)
+ {
+ struct riscv_elf_dyn_relocs **pp;
+ struct riscv_elf_dyn_relocs *p;
+
+ /* Add reloc counts against the indirect sym to the direct sym
+ list. Merge any entries against the same section. */
+ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
+ {
+ struct riscv_elf_dyn_relocs *q;
+
+ for (q = edir->dyn_relocs; q != NULL; q = q->next)
+ if (q->sec == p->sec)
+ {
+ q->pc_count += p->pc_count;
+ q->count += p->count;
+ *pp = p->next;
+ break;
+ }
+ if (q == NULL)
+ pp = &p->next;
+ }
+ *pp = edir->dyn_relocs;
+ }
+
+ edir->dyn_relocs = eind->dyn_relocs;
+ eind->dyn_relocs = NULL;
+ }
+
+ if (ind->root.type == bfd_link_hash_indirect
+ && dir->got.refcount <= 0)
+ {
+ edir->tls_type = eind->tls_type;
+ eind->tls_type = GOT_UNKNOWN;
+ }
+ _bfd_elf_link_hash_copy_indirect (info, dir, ind);
+}
+
+static bfd_boolean
+riscv_elf_record_tls_type (bfd *abfd, struct elf_link_hash_entry *h,
+ unsigned long symndx, char tls_type)
+{
+ char *new_tls_type = &_bfd_riscv_elf_tls_type (abfd, h, symndx);
+ *new_tls_type |= tls_type;
+ if ((*new_tls_type & GOT_NORMAL) && (*new_tls_type & ~GOT_NORMAL))
+ {
+ (*_bfd_error_handler)
+ (_("%B: `%s' accessed both as normal and thread local symbol"),
+ abfd, h ? h->root.root.string : "<local>");
+ return FALSE;
+ }
+ return TRUE;
+}
+
+static bfd_boolean
+riscv_elf_record_got_reference (bfd *abfd, struct bfd_link_info *info,
+ struct elf_link_hash_entry *h, long symndx)
+{
+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+
+ if (htab->elf.sgot == NULL)
+ {
+ if (!riscv_elf_create_got_section (htab->elf.dynobj, info))
+ return FALSE;
+ }
+
+ if (h != NULL)
+ {
+ h->got.refcount += 1;
+ return TRUE;
+ }
+
+ /* This is a global offset table entry for a local symbol. */
+ if (elf_local_got_refcounts (abfd) == NULL)
+ {
+ bfd_size_type size = symtab_hdr->sh_info * (sizeof (bfd_vma) + 1);
+ if (!(elf_local_got_refcounts (abfd) = bfd_zalloc (abfd, size)))
+ return FALSE;
+ _bfd_riscv_elf_local_got_tls_type (abfd)
+ = (char *) (elf_local_got_refcounts (abfd) + symtab_hdr->sh_info);
+ }
+ elf_local_got_refcounts (abfd) [symndx] += 1;
+
+ return TRUE;
+}
+
+static bfd_boolean
+bad_static_reloc (bfd *abfd, unsigned r_type, struct elf_link_hash_entry *h)
+{
+ (*_bfd_error_handler)
+ (_("%B: relocation %s against `%s' can not be used when making a shared "
+ "object; recompile with -fPIC"),
+ abfd, riscv_elf_rtype_to_howto (r_type)->name,
+ h != NULL ? h->root.root.string : "a local symbol");
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+}
+/* Look through the relocs for a section during the first phase, and
+ allocate space in the global offset table or procedure linkage
+ table. */
+
+static bfd_boolean
+riscv_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
+ asection *sec, const Elf_Internal_Rela *relocs)
+{
+ struct riscv_elf_link_hash_table *htab;
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ const Elf_Internal_Rela *rel;
+ asection *sreloc = NULL;
+
+ if (bfd_link_relocatable (info))
+ return TRUE;
+
+ htab = riscv_elf_hash_table (info);
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (abfd);
+
+ if (htab->elf.dynobj == NULL)
+ htab->elf.dynobj = abfd;
+
+ for (rel = relocs; rel < relocs + sec->reloc_count; rel++)
+ {
+ unsigned int r_type;
+ unsigned long r_symndx;
+ struct elf_link_hash_entry *h;
+
+ r_symndx = ELFNN_R_SYM (rel->r_info);
+ r_type = ELFNN_R_TYPE (rel->r_info);
+
+ if (r_symndx >= NUM_SHDR_ENTRIES (symtab_hdr))
+ {
+ (*_bfd_error_handler) (_("%B: bad symbol index: %d"),
+ abfd, r_symndx);
+ return FALSE;
+ }
+
+ if (r_symndx < symtab_hdr->sh_info)
+ h = NULL;
+ else
+ {
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ /* PR15323, ref flags aren't set for references in the same
+ object. */
+ h->root.non_ir_ref = 1;
+ }
+
+ switch (r_type)
+ {
+ case R_RISCV_TLS_GD_HI20:
+ if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx)
+ || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_GD))
+ return FALSE;
+ break;
+
+ case R_RISCV_TLS_GOT_HI20:
+ if (bfd_link_pic (info))
+ info->flags |= DF_STATIC_TLS;
+ if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx)
+ || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_IE))
+ return FALSE;
+ break;
+
+ case R_RISCV_GOT_HI20:
+ if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx)
+ || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_NORMAL))
+ return FALSE;
+ break;
+
+ case R_RISCV_CALL_PLT:
+ /* This symbol requires a procedure linkage table entry. We
+ actually build the entry in adjust_dynamic_symbol,
+ because this might be a case of linking PIC code without
+ linking in any dynamic objects, in which case we don't
+ need to generate a procedure linkage table after all. */
+
+ if (h != NULL)
+ {
+ h->needs_plt = 1;
+ h->plt.refcount += 1;
+ }
+ break;
+
+ case R_RISCV_CALL:
+ case R_RISCV_JAL:
+ case R_RISCV_BRANCH:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_PCREL_HI20:
+ /* In shared libraries, these relocs are known to bind locally. */
+ if (bfd_link_pic (info))
+ break;
+ goto static_reloc;
+
+ case R_RISCV_TPREL_HI20:
+ if (!bfd_link_executable (info))
+ return bad_static_reloc (abfd, r_type, h);
+ if (h != NULL)
+ riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_LE);
+ goto static_reloc;
+
+ case R_RISCV_HI20:
+ if (bfd_link_pic (info))
+ return bad_static_reloc (abfd, r_type, h);
+ /* Fall through. */
+
+ case R_RISCV_COPY:
+ case R_RISCV_JUMP_SLOT:
+ case R_RISCV_RELATIVE:
+ case R_RISCV_64:
+ case R_RISCV_32:
+ /* Fall through. */
+
+ static_reloc:
+ /* This reloc might not bind locally. */
+ if (h != NULL)
+ h->non_got_ref = 1;
+
+ if (h != NULL && !bfd_link_pic (info))
+ {
+ /* We may need a .plt entry if the function this reloc
+ refers to is in a shared lib. */
+ h->plt.refcount += 1;
+ }
+
+ /* If we are creating a shared library, and this is a reloc
+ against a global symbol, or a non PC relative reloc
+ against a local symbol, then we need to copy the reloc
+ into the shared library. However, if we are linking with
+ -Bsymbolic, we do not need to copy a reloc against a
+ global symbol which is defined in an object we are
+ including in the link (i.e., DEF_REGULAR is set). At
+ this point we have not seen all the input files, so it is
+ possible that DEF_REGULAR is not set now but will be set
+ later (it is never cleared). In case of a weak definition,
+ DEF_REGULAR may be cleared later by a strong definition in
+ a shared library. We account for that possibility below by
+ storing information in the relocs_copied field of the hash
+ table entry. A similar situation occurs when creating
+ shared libraries and symbol visibility changes render the
+ symbol local.
+
+ If on the other hand, we are creating an executable, we
+ may need to keep relocations for symbols satisfied by a
+ dynamic library if we manage to avoid copy relocs for the
+ symbol. */
+ if ((bfd_link_pic (info)
+ && (sec->flags & SEC_ALLOC) != 0
+ && (! riscv_elf_rtype_to_howto (r_type)->pc_relative
+ || (h != NULL
+ && (! info->symbolic
+ || h->root.type == bfd_link_hash_defweak
+ || !h->def_regular))))
+ || (!bfd_link_pic (info)
+ && (sec->flags & SEC_ALLOC) != 0
+ && h != NULL
+ && (h->root.type == bfd_link_hash_defweak
+ || !h->def_regular)))
+ {
+ struct riscv_elf_dyn_relocs *p;
+ struct riscv_elf_dyn_relocs **head;
+
+ /* When creating a shared object, we must copy these
+ relocs into the output file. We create a reloc
+ section in dynobj and make room for the reloc. */
+ if (sreloc == NULL)
+ {
+ sreloc = _bfd_elf_make_dynamic_reloc_section
+ (sec, htab->elf.dynobj, RISCV_ELF_LOG_WORD_BYTES,
+ abfd, /*rela?*/ TRUE);
+
+ if (sreloc == NULL)
+ return FALSE;
+ }
+
+ /* If this is a global symbol, we count the number of
+ relocations we need for this symbol. */
+ if (h != NULL)
+ head = &((struct riscv_elf_link_hash_entry *) h)->dyn_relocs;
+ else
+ {
+ /* Track dynamic relocs needed for local syms too.
+ We really need local syms available to do this
+ easily. Oh well. */
+
+ asection *s;
+ void *vpp;
+ Elf_Internal_Sym *isym;
+
+ isym = bfd_sym_from_r_symndx (&htab->sym_cache,
+ abfd, r_symndx);
+ if (isym == NULL)
+ return FALSE;
+
+ s = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ if (s == NULL)
+ s = sec;
+
+ vpp = &elf_section_data (s)->local_dynrel;
+ head = (struct riscv_elf_dyn_relocs **) vpp;
+ }
+
+ p = *head;
+ if (p == NULL || p->sec != sec)
+ {
+ bfd_size_type amt = sizeof *p;
+ p = ((struct riscv_elf_dyn_relocs *)
+ bfd_alloc (htab->elf.dynobj, amt));
+ if (p == NULL)
+ return FALSE;
+ p->next = *head;
+ *head = p;
+ p->sec = sec;
+ p->count = 0;
+ p->pc_count = 0;
+ }
+
+ p->count += 1;
+ p->pc_count += riscv_elf_rtype_to_howto (r_type)->pc_relative;
+ }
+
+ break;
+
+ case R_RISCV_GNU_VTINHERIT:
+ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
+ return FALSE;
+ break;
+
+ case R_RISCV_GNU_VTENTRY:
+ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
+ return FALSE;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ return TRUE;
+}
+
+static asection *
+riscv_elf_gc_mark_hook (asection *sec,
+ struct bfd_link_info *info,
+ Elf_Internal_Rela *rel,
+ struct elf_link_hash_entry *h,
+ Elf_Internal_Sym *sym)
+{
+ if (h != NULL)
+ switch (ELFNN_R_TYPE (rel->r_info))
+ {
+ case R_RISCV_GNU_VTINHERIT:
+ case R_RISCV_GNU_VTENTRY:
+ return NULL;
+ }
+
+ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
+}
+
+/* Update the got entry reference counts for the section being removed. */
+static bfd_boolean
+riscv_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info,
+ asection *sec, const Elf_Internal_Rela *relocs)
+{
+ const Elf_Internal_Rela *rel, *relend;
+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd);
+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd);
+ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
+
+ if (bfd_link_relocatable (info))
+ return TRUE;
+
+ elf_section_data (sec)->local_dynrel = NULL;
+
+ for (rel = relocs, relend = relocs + sec->reloc_count; rel < relend; rel++)
+ {
+ unsigned long r_symndx;
+ struct elf_link_hash_entry *h = NULL;
+
+ r_symndx = ELFNN_R_SYM (rel->r_info);
+ if (r_symndx >= symtab_hdr->sh_info)
+ {
+ struct riscv_elf_link_hash_entry *eh;
+ struct riscv_elf_dyn_relocs **pp;
+ struct riscv_elf_dyn_relocs *p;
+
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+ eh = (struct riscv_elf_link_hash_entry *) h;
+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next)
+ if (p->sec == sec)
+ {
+ /* Everything must go for SEC. */
+ *pp = p->next;
+ break;
+ }
+ }
+
+ switch (ELFNN_R_TYPE (rel->r_info))
+ {
+ case R_RISCV_GOT_HI20:
+ case R_RISCV_TLS_GOT_HI20:
+ case R_RISCV_TLS_GD_HI20:
+ if (h != NULL)
+ {
+ if (h->got.refcount > 0)
+ h->got.refcount--;
+ }
+ else
+ {
+ if (local_got_refcounts &&
+ local_got_refcounts[r_symndx] > 0)
+ local_got_refcounts[r_symndx]--;
+ }
+ break;
+
+ case R_RISCV_HI20:
+ case R_RISCV_PCREL_HI20:
+ case R_RISCV_COPY:
+ case R_RISCV_JUMP_SLOT:
+ case R_RISCV_RELATIVE:
+ case R_RISCV_64:
+ case R_RISCV_32:
+ case R_RISCV_BRANCH:
+ case R_RISCV_CALL:
+ case R_RISCV_JAL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ if (bfd_link_pic (info))
+ break;
+ /* Fall through. */
+
+ case R_RISCV_CALL_PLT:
+ if (h != NULL)
+ {
+ if (h->plt.refcount > 0)
+ h->plt.refcount--;
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Adjust a symbol defined by a dynamic object and referenced by a
+ regular object. The current definition is in some section of the
+ dynamic object, but we're not including those sections. We have to
+ change the definition to something the rest of the link can
+ understand. */
+
+static bfd_boolean
+riscv_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *h)
+{
+ struct riscv_elf_link_hash_table *htab;
+ struct riscv_elf_link_hash_entry * eh;
+ struct riscv_elf_dyn_relocs *p;
+ bfd *dynobj;
+ asection *s;
+
+ htab = riscv_elf_hash_table (info);
+ BFD_ASSERT (htab != NULL);
+
+ dynobj = htab->elf.dynobj;
+
+ /* Make sure we know what is going on here. */
+ BFD_ASSERT (dynobj != NULL
+ && (h->needs_plt
+ || h->type == STT_GNU_IFUNC
+ || h->u.weakdef != NULL
+ || (h->def_dynamic
+ && h->ref_regular
+ && !h->def_regular)));
+
+ /* If this is a function, put it in the procedure linkage table. We
+ will fill in the contents of the procedure linkage table later
+ (although we could actually do it here). */
+ if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
+ {
+ if (h->plt.refcount <= 0
+ || SYMBOL_CALLS_LOCAL (info, h)
+ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
+ && h->root.type == bfd_link_hash_undefweak))
+ {
+ /* This case can occur if we saw a R_RISCV_CALL_PLT reloc in an
+ input file, but the symbol was never referred to by a dynamic
+ object, or if all references were garbage collected. In such
+ a case, we don't actually need to build a PLT entry. */
+ h->plt.offset = (bfd_vma) -1;
+ h->needs_plt = 0;
+ }
+
+ return TRUE;
+ }
+ else
+ h->plt.offset = (bfd_vma) -1;
+
+ /* If this is a weak symbol, and there is a real definition, the
+ processor independent code will have arranged for us to see the
+ real definition first, and we can just use the same value. */
+ if (h->u.weakdef != NULL)
+ {
+ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
+ || h->u.weakdef->root.type == bfd_link_hash_defweak);
+ h->root.u.def.section = h->u.weakdef->root.u.def.section;
+ h->root.u.def.value = h->u.weakdef->root.u.def.value;
+ return TRUE;
+ }
+
+ /* This is a reference to a symbol defined by a dynamic object which
+ is not a function. */
+
+ /* If we are creating a shared library, we must presume that the
+ only references to the symbol are via the global offset table.
+ For such cases we need not do anything here; the relocations will
+ be handled correctly by relocate_section. */
+ if (bfd_link_pic (info))
+ return TRUE;
+
+ /* If there are no references to this symbol that do not use the
+ GOT, we don't need to generate a copy reloc. */
+ if (!h->non_got_ref)
+ return TRUE;
+
+ /* If -z nocopyreloc was given, we won't generate them either. */
+ if (info->nocopyreloc)
+ {
+ h->non_got_ref = 0;
+ return TRUE;
+ }
+
+ eh = (struct riscv_elf_link_hash_entry *) h;
+ for (p = eh->dyn_relocs; p != NULL; p = p->next)
+ {
+ s = p->sec->output_section;
+ if (s != NULL && (s->flags & SEC_READONLY) != 0)
+ break;
+ }
+
+ /* If we didn't find any dynamic relocs in read-only sections, then
+ we'll be keeping the dynamic relocs and avoiding the copy reloc. */
+ if (p == NULL)
+ {
+ h->non_got_ref = 0;
+ return TRUE;
+ }
+
+ /* We must allocate the symbol in our .dynbss section, which will
+ become part of the .bss section of the executable. There will be
+ an entry for this symbol in the .dynsym section. The dynamic
+ object will contain position independent code, so all references
+ from the dynamic object to this symbol will go through the global
+ offset table. The dynamic linker will use the .dynsym entry to
+ determine the address it must put in the global offset table, so
+ both the dynamic object and the regular object will refer to the
+ same memory location for the variable. */
+
+ /* We must generate a R_RISCV_COPY reloc to tell the dynamic linker
+ to copy the initial value out of the dynamic object and into the
+ runtime process image. We need to remember the offset into the
+ .rel.bss section we are going to use. */
+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0)
+ {
+ htab->srelbss->size += sizeof (ElfNN_External_Rela);
+ h->needs_copy = 1;
+ }
+
+ if (eh->tls_type & ~GOT_NORMAL)
+ return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdyntdata);
+
+ return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdynbss);
+}
+
+/* Allocate space in .plt, .got and associated reloc sections for
+ dynamic relocs. */
+
+static bfd_boolean
+allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
+{
+ struct bfd_link_info *info;
+ struct riscv_elf_link_hash_table *htab;
+ struct riscv_elf_link_hash_entry *eh;
+ struct riscv_elf_dyn_relocs *p;
+
+ if (h->root.type == bfd_link_hash_indirect)
+ return TRUE;
+
+ info = (struct bfd_link_info *) inf;
+ htab = riscv_elf_hash_table (info);
+ BFD_ASSERT (htab != NULL);
+
+ if (htab->elf.dynamic_sections_created
+ && h->plt.refcount > 0)
+ {
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (h->dynindx == -1
+ && !h->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
+ {
+ asection *s = htab->elf.splt;
+
+ if (s->size == 0)
+ s->size = PLT_HEADER_SIZE;
+
+ h->plt.offset = s->size;
+
+ /* Make room for this entry. */
+ s->size += PLT_ENTRY_SIZE;
+
+ /* We also need to make an entry in the .got.plt section. */
+ htab->elf.sgotplt->size += GOT_ENTRY_SIZE;
+
+ /* We also need to make an entry in the .rela.plt section. */
+ htab->elf.srelplt->size += sizeof (ElfNN_External_Rela);
+
+ /* If this symbol is not defined in a regular file, and we are
+ not generating a shared library, then set the symbol to this
+ location in the .plt. This is required to make function
+ pointers compare as equal between the normal executable and
+ the shared library. */
+ if (! bfd_link_pic (info)
+ && !h->def_regular)
+ {
+ h->root.u.def.section = s;
+ h->root.u.def.value = h->plt.offset;
+ }
+ }
+ else
+ {
+ h->plt.offset = (bfd_vma) -1;
+ h->needs_plt = 0;
+ }
+ }
+ else
+ {
+ h->plt.offset = (bfd_vma) -1;
+ h->needs_plt = 0;
+ }
+
+ if (h->got.refcount > 0)
+ {
+ asection *s;
+ bfd_boolean dyn;
+ int tls_type = riscv_elf_hash_entry (h)->tls_type;
+
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (h->dynindx == -1
+ && !h->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ s = htab->elf.sgot;
+ h->got.offset = s->size;
+ dyn = htab->elf.dynamic_sections_created;
+ if (tls_type & (GOT_TLS_GD | GOT_TLS_IE))
+ {
+ /* TLS_GD needs two dynamic relocs and two GOT slots. */
+ if (tls_type & GOT_TLS_GD)
+ {
+ s->size += 2 * RISCV_ELF_WORD_BYTES;
+ htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela);
+ }
+
+ /* TLS_IE needs one dynamic reloc and one GOT slot. */
+ if (tls_type & GOT_TLS_IE)
+ {
+ s->size += RISCV_ELF_WORD_BYTES;
+ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela);
+ }
+ }
+ else
+ {
+ s->size += RISCV_ELF_WORD_BYTES;
+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, bfd_link_pic (info), h))
+ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela);
+ }
+ }
+ else
+ h->got.offset = (bfd_vma) -1;
+
+ eh = (struct riscv_elf_link_hash_entry *) h;
+ if (eh->dyn_relocs == NULL)
+ return TRUE;
+
+ /* In the shared -Bsymbolic case, discard space allocated for
+ dynamic pc-relative relocs against symbols which turn out to be
+ defined in regular objects. For the normal shared case, discard
+ space for pc-relative relocs that have become local due to symbol
+ visibility changes. */
+
+ if (bfd_link_pic (info))
+ {
+ if (SYMBOL_CALLS_LOCAL (info, h))
+ {
+ struct riscv_elf_dyn_relocs **pp;
+
+ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
+ {
+ p->count -= p->pc_count;
+ p->pc_count = 0;
+ if (p->count == 0)
+ *pp = p->next;
+ else
+ pp = &p->next;
+ }
+ }
+
+ /* Also discard relocs on undefined weak syms with non-default
+ visibility. */
+ if (eh->dyn_relocs != NULL
+ && h->root.type == bfd_link_hash_undefweak)
+ {
+ if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
+ eh->dyn_relocs = NULL;
+
+ /* Make sure undefined weak symbols are output as a dynamic
+ symbol in PIEs. */
+ else if (h->dynindx == -1
+ && !h->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+ }
+ }
+ else
+ {
+ /* For the non-shared case, discard space for relocs against
+ symbols which turn out to need copy relocs or are not
+ dynamic. */
+
+ if (!h->non_got_ref
+ && ((h->def_dynamic
+ && !h->def_regular)
+ || (htab->elf.dynamic_sections_created
+ && (h->root.type == bfd_link_hash_undefweak
+ || h->root.type == bfd_link_hash_undefined))))
+ {
+ /* Make sure this symbol is output as a dynamic symbol.
+ Undefined weak syms won't yet be marked as dynamic. */
+ if (h->dynindx == -1
+ && !h->forced_local)
+ {
+ if (! bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+ }
+
+ /* If that succeeded, we know we'll be keeping all the
+ relocs. */
+ if (h->dynindx != -1)
+ goto keep;
+ }
+
+ eh->dyn_relocs = NULL;
+
+ keep: ;
+ }
+
+ /* Finally, allocate space. */
+ for (p = eh->dyn_relocs; p != NULL; p = p->next)
+ {
+ asection *sreloc = elf_section_data (p->sec)->sreloc;
+ sreloc->size += p->count * sizeof (ElfNN_External_Rela);
+ }
+
+ return TRUE;
+}
+
+/* Find any dynamic relocs that apply to read-only sections. */
+
+static bfd_boolean
+readonly_dynrelocs (struct elf_link_hash_entry *h, void *inf)
+{
+ struct riscv_elf_link_hash_entry *eh;
+ struct riscv_elf_dyn_relocs *p;
+
+ eh = (struct riscv_elf_link_hash_entry *) h;
+ for (p = eh->dyn_relocs; p != NULL; p = p->next)
+ {
+ asection *s = p->sec->output_section;
+
+ if (s != NULL && (s->flags & SEC_READONLY) != 0)
+ {
+ ((struct bfd_link_info *) inf)->flags |= DF_TEXTREL;
+ return FALSE;
+ }
+ }
+ return TRUE;
+}
+
+static bfd_boolean
+riscv_elf_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+{
+ struct riscv_elf_link_hash_table *htab;
+ bfd *dynobj;
+ asection *s;
+ bfd *ibfd;
+
+ htab = riscv_elf_hash_table (info);
+ BFD_ASSERT (htab != NULL);
+ dynobj = htab->elf.dynobj;
+ BFD_ASSERT (dynobj != NULL);
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+ if (bfd_link_executable (info) && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+ s->size = strlen (ELFNN_DYNAMIC_INTERPRETER) + 1;
+ s->contents = (unsigned char *) ELFNN_DYNAMIC_INTERPRETER;
+ }
+ }
+
+ /* Set up .got offsets for local syms, and space for local dynamic
+ relocs. */
+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
+ {
+ bfd_signed_vma *local_got;
+ bfd_signed_vma *end_local_got;
+ char *local_tls_type;
+ bfd_size_type locsymcount;
+ Elf_Internal_Shdr *symtab_hdr;
+ asection *srel;
+
+ if (! is_riscv_elf (ibfd))
+ continue;
+
+ for (s = ibfd->sections; s != NULL; s = s->next)
+ {
+ struct riscv_elf_dyn_relocs *p;
+
+ for (p = elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
+ {
+ if (!bfd_is_abs_section (p->sec)
+ && bfd_is_abs_section (p->sec->output_section))
+ {
+ /* Input section has been discarded, either because
+ it is a copy of a linkonce section or due to
+ linker script /DISCARD/, so we'll be discarding
+ the relocs too. */
+ }
+ else if (p->count != 0)
+ {
+ srel = elf_section_data (p->sec)->sreloc;
+ srel->size += p->count * sizeof (ElfNN_External_Rela);
+ if ((p->sec->output_section->flags & SEC_READONLY) != 0)
+ info->flags |= DF_TEXTREL;
+ }
+ }
+ }
+
+ local_got = elf_local_got_refcounts (ibfd);
+ if (!local_got)
+ continue;
+
+ symtab_hdr = &elf_symtab_hdr (ibfd);
+ locsymcount = symtab_hdr->sh_info;
+ end_local_got = local_got + locsymcount;
+ local_tls_type = _bfd_riscv_elf_local_got_tls_type (ibfd);
+ s = htab->elf.sgot;
+ srel = htab->elf.srelgot;
+ for (; local_got < end_local_got; ++local_got, ++local_tls_type)
+ {
+ if (*local_got > 0)
+ {
+ *local_got = s->size;
+ s->size += RISCV_ELF_WORD_BYTES;
+ if (*local_tls_type & GOT_TLS_GD)
+ s->size += RISCV_ELF_WORD_BYTES;
+ if (bfd_link_pic (info)
+ || (*local_tls_type & (GOT_TLS_GD | GOT_TLS_IE)))
+ srel->size += sizeof (ElfNN_External_Rela);
+ }
+ else
+ *local_got = (bfd_vma) -1;
+ }
+ }
+
+ /* Allocate global sym .plt and .got entries, and space for global
+ sym dynamic relocs. */
+ elf_link_hash_traverse (&htab->elf, allocate_dynrelocs, info);
+
+ if (htab->elf.sgotplt)
+ {
+ struct elf_link_hash_entry *got;
+ got = elf_link_hash_lookup (elf_hash_table (info),
+ "_GLOBAL_OFFSET_TABLE_",
+ FALSE, FALSE, FALSE);
+
+ /* Don't allocate .got.plt section if there are no GOT nor PLT
+ entries and there is no refeence to _GLOBAL_OFFSET_TABLE_. */
+ if ((got == NULL
+ || !got->ref_regular_nonweak)
+ && (htab->elf.sgotplt->size == GOTPLT_HEADER_SIZE)
+ && (htab->elf.splt == NULL
+ || htab->elf.splt->size == 0)
+ && (htab->elf.sgot == NULL
+ || (htab->elf.sgot->size
+ == get_elf_backend_data (output_bfd)->got_header_size)))
+ htab->elf.sgotplt->size = 0;
+ }
+
+ /* The check_relocs and adjust_dynamic_symbol entry points have
+ determined the sizes of the various dynamic sections. Allocate
+ memory for them. */
+ for (s = dynobj->sections; s != NULL; s = s->next)
+ {
+ if ((s->flags & SEC_LINKER_CREATED) == 0)
+ continue;
+
+ if (s == htab->elf.splt
+ || s == htab->elf.sgot
+ || s == htab->elf.sgotplt
+ || s == htab->sdynbss)
+ {
+ /* Strip this section if we don't need it; see the
+ comment below. */
+ }
+ else if (strncmp (s->name, ".rela", 5) == 0)
+ {
+ if (s->size != 0)
+ {
+ /* We use the reloc_count field as a counter if we need
+ to copy relocs into the output file. */
+ s->reloc_count = 0;
+ }
+ }
+ else
+ {
+ /* It's not one of our sections. */
+ continue;
+ }
+
+ if (s->size == 0)
+ {
+ /* If we don't need this section, strip it from the
+ output file. This is mostly to handle .rela.bss and
+ .rela.plt. We must create both sections in
+ create_dynamic_sections, because they must be created
+ before the linker maps input sections to output
+ sections. The linker does that before
+ adjust_dynamic_symbol is called, and it is that
+ function which decides whether anything needs to go
+ into these sections. */
+ s->flags |= SEC_EXCLUDE;
+ continue;
+ }
+
+ if ((s->flags & SEC_HAS_CONTENTS) == 0)
+ continue;
+
+ /* Allocate memory for the section contents. Zero the memory
+ for the benefit of .rela.plt, which has 4 unused entries
+ at the beginning, and we don't want garbage. */
+ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
+ if (s->contents == NULL)
+ return FALSE;
+ }
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Add some entries to the .dynamic section. We fill in the
+ values later, in riscv_elf_finish_dynamic_sections, but we
+ must add the entries now so that we get the correct size for
+ the .dynamic section. The DT_DEBUG entry is filled in by the
+ dynamic linker and used by the debugger. */
+#define add_dynamic_entry(TAG, VAL) \
+ _bfd_elf_add_dynamic_entry (info, TAG, VAL)
+
+ if (bfd_link_executable (info))
+ {
+ if (!add_dynamic_entry (DT_DEBUG, 0))
+ return FALSE;
+ }
+
+ if (htab->elf.srelplt->size != 0)
+ {
+ if (!add_dynamic_entry (DT_PLTGOT, 0)
+ || !add_dynamic_entry (DT_PLTRELSZ, 0)
+ || !add_dynamic_entry (DT_PLTREL, DT_RELA)
+ || !add_dynamic_entry (DT_JMPREL, 0))
+ return FALSE;
+ }
+
+ if (!add_dynamic_entry (DT_RELA, 0)
+ || !add_dynamic_entry (DT_RELASZ, 0)
+ || !add_dynamic_entry (DT_RELAENT, sizeof (ElfNN_External_Rela)))
+ return FALSE;
+
+ /* If any dynamic relocs apply to a read-only section,
+ then we need a DT_TEXTREL entry. */
+ if ((info->flags & DF_TEXTREL) == 0)
+ elf_link_hash_traverse (&htab->elf, readonly_dynrelocs, info);
+
+ if (info->flags & DF_TEXTREL)
+ {
+ if (!add_dynamic_entry (DT_TEXTREL, 0))
+ return FALSE;
+ }
+ }
+#undef add_dynamic_entry
+
+ return TRUE;
+}
+
+#define TP_OFFSET 0
+#define DTP_OFFSET 0x800
+
+/* Return the relocation value for a TLS dtp-relative reloc. */
+
+static bfd_vma
+dtpoff (struct bfd_link_info *info, bfd_vma address)
+{
+ /* If tls_sec is NULL, we should have signalled an error already. */
+ if (elf_hash_table (info)->tls_sec == NULL)
+ return 0;
+ return address - elf_hash_table (info)->tls_sec->vma - DTP_OFFSET;
+}
+
+/* Return the relocation value for a static TLS tp-relative relocation. */
+
+static bfd_vma
+tpoff (struct bfd_link_info *info, bfd_vma address)
+{
+ /* If tls_sec is NULL, we should have signalled an error already. */
+ if (elf_hash_table (info)->tls_sec == NULL)
+ return 0;
+ return address - elf_hash_table (info)->tls_sec->vma - TP_OFFSET;
+}
+
+/* Return the global pointer's value, or 0 if it is not in use. */
+
+static bfd_vma
+riscv_global_pointer_value (struct bfd_link_info *info)
+{
+ struct bfd_link_hash_entry *h;
+
+ h = bfd_link_hash_lookup (info->hash, "_gp", FALSE, FALSE, TRUE);
+ if (h == NULL || h->type != bfd_link_hash_defined)
+ return 0;
+
+ return h->u.def.value + sec_addr (h->u.def.section);
+}
+
+/* Emplace a static relocation. */
+
+static bfd_reloc_status_type
+perform_relocation (const reloc_howto_type *howto,
+ const Elf_Internal_Rela *rel,
+ bfd_vma value,
+ asection *input_section,
+ bfd *input_bfd,
+ bfd_byte *contents)
+{
+ if (howto->pc_relative)
+ value -= sec_addr (input_section) + rel->r_offset;
+ value += rel->r_addend;
+
+ switch (ELFNN_R_TYPE (rel->r_info))
+ {
+ case R_RISCV_HI20:
+ case R_RISCV_TPREL_HI20:
+ case R_RISCV_PCREL_HI20:
+ case R_RISCV_GOT_HI20:
+ case R_RISCV_TLS_GOT_HI20:
+ case R_RISCV_TLS_GD_HI20:
+ if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
+ return bfd_reloc_overflow;
+ value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
+ break;
+
+ case R_RISCV_LO12_I:
+ case R_RISCV_GPREL_I:
+ case R_RISCV_TPREL_LO12_I:
+ case R_RISCV_PCREL_LO12_I:
+ value = ENCODE_ITYPE_IMM (value);
+ break;
+
+ case R_RISCV_LO12_S:
+ case R_RISCV_GPREL_S:
+ case R_RISCV_TPREL_LO12_S:
+ case R_RISCV_PCREL_LO12_S:
+ value = ENCODE_STYPE_IMM (value);
+ break;
+
+ case R_RISCV_CALL:
+ case R_RISCV_CALL_PLT:
+ if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
+ return bfd_reloc_overflow;
+ value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))
+ | (ENCODE_ITYPE_IMM (value) << 32);
+ break;
+
+ case R_RISCV_JAL:
+ if (!VALID_UJTYPE_IMM (value))
+ return bfd_reloc_overflow;
+ value = ENCODE_UJTYPE_IMM (value);
+ break;
+
+ case R_RISCV_BRANCH:
+ if (!VALID_SBTYPE_IMM (value))
+ return bfd_reloc_overflow;
+ value = ENCODE_SBTYPE_IMM (value);
+ break;
+
+ case R_RISCV_RVC_BRANCH:
+ if (!VALID_RVC_B_IMM (value))
+ return bfd_reloc_overflow;
+ value = ENCODE_RVC_B_IMM (value);
+ break;
+
+ case R_RISCV_RVC_JUMP:
+ if (!VALID_RVC_J_IMM (value))
+ return bfd_reloc_overflow;
+ value = ENCODE_RVC_J_IMM (value);
+ break;
+
+ case R_RISCV_RVC_LUI:
+ if (!VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value)))
+ return bfd_reloc_overflow;
+ value = ENCODE_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value));
+ break;
+
+ case R_RISCV_32:
+ case R_RISCV_64:
+ case R_RISCV_ADD8:
+ case R_RISCV_ADD16:
+ case R_RISCV_ADD32:
+ case R_RISCV_ADD64:
+ case R_RISCV_SUB8:
+ case R_RISCV_SUB16:
+ case R_RISCV_SUB32:
+ case R_RISCV_SUB64:
+ case R_RISCV_TLS_DTPREL32:
+ case R_RISCV_TLS_DTPREL64:
+ break;
+
+ default:
+ return bfd_reloc_notsupported;
+ }
+
+ bfd_vma word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset);
+ word = (word & ~howto->dst_mask) | (value & howto->dst_mask);
+ bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset);
+
+ return bfd_reloc_ok;
+}
+
+/* Remember all PC-relative high-part relocs we've encountered to help us
+ later resolve the corresponding low-part relocs. */
+
+typedef struct {
+ bfd_vma address;
+ bfd_vma value;
+} riscv_pcrel_hi_reloc;
+
+typedef struct riscv_pcrel_lo_reloc {
+ asection *input_section;
+ struct bfd_link_info *info;
+ reloc_howto_type *howto;
+ const Elf_Internal_Rela *reloc;
+ bfd_vma addr;
+ const char *name;
+ bfd_byte *contents;
+ struct riscv_pcrel_lo_reloc *next;
+} riscv_pcrel_lo_reloc;
+
+typedef struct {
+ htab_t hi_relocs;
+ riscv_pcrel_lo_reloc *lo_relocs;
+} riscv_pcrel_relocs;
+
+static hashval_t
+riscv_pcrel_reloc_hash (const void *entry)
+{
+ const riscv_pcrel_hi_reloc *e = entry;
+ return (hashval_t)(e->address >> 2);
+}
+
+static bfd_boolean
+riscv_pcrel_reloc_eq (const void *entry1, const void *entry2)
+{
+ const riscv_pcrel_hi_reloc *e1 = entry1, *e2 = entry2;
+ return e1->address == e2->address;
+}
+
+static bfd_boolean
+riscv_init_pcrel_relocs (riscv_pcrel_relocs *p)
+{
+
+ p->lo_relocs = NULL;
+ p->hi_relocs = htab_create (1024, riscv_pcrel_reloc_hash,
+ riscv_pcrel_reloc_eq, free);
+ return p->hi_relocs != NULL;
+}
+
+static void
+riscv_free_pcrel_relocs (riscv_pcrel_relocs *p)
+{
+ riscv_pcrel_lo_reloc *cur = p->lo_relocs;
+ while (cur != NULL)
+ {
+ riscv_pcrel_lo_reloc *next = cur->next;
+ free (cur);
+ cur = next;
+ }
+
+ htab_delete (p->hi_relocs);
+}
+
+static bfd_boolean
+riscv_record_pcrel_hi_reloc (riscv_pcrel_relocs *p, bfd_vma addr, bfd_vma value)
+{
+ riscv_pcrel_hi_reloc entry = {addr, value - addr};
+ riscv_pcrel_hi_reloc **slot =
+ (riscv_pcrel_hi_reloc **) htab_find_slot (p->hi_relocs, &entry, INSERT);
+ BFD_ASSERT (*slot == NULL);
+ *slot = (riscv_pcrel_hi_reloc *) bfd_malloc (sizeof (riscv_pcrel_hi_reloc));
+ if (*slot == NULL)
+ return FALSE;
+ **slot = entry;
+ return TRUE;
+}
+
+static bfd_boolean
+riscv_record_pcrel_lo_reloc (riscv_pcrel_relocs *p,
+ asection *input_section,
+ struct bfd_link_info *info,
+ reloc_howto_type *howto,
+ const Elf_Internal_Rela *reloc,
+ bfd_vma addr,
+ const char *name,
+ bfd_byte *contents)
+{
+ riscv_pcrel_lo_reloc *entry;
+ entry = (riscv_pcrel_lo_reloc *) bfd_malloc (sizeof (riscv_pcrel_lo_reloc));
+ if (entry == NULL)
+ return FALSE;
+ *entry = (riscv_pcrel_lo_reloc) {input_section, info, howto, reloc, addr,
+ name, contents, p->lo_relocs};
+ p->lo_relocs = entry;
+ return TRUE;
+}
+
+static bfd_boolean
+riscv_resolve_pcrel_lo_relocs (riscv_pcrel_relocs *p)
+{
+ riscv_pcrel_lo_reloc *r;
+ for (r = p->lo_relocs; r != NULL; r = r->next)
+ {
+ bfd *input_bfd = r->input_section->owner;
+ riscv_pcrel_hi_reloc search = {r->addr, 0};
+ riscv_pcrel_hi_reloc *entry = htab_find (p->hi_relocs, &search);
+ if (entry == NULL)
+ {
+ ((*r->info->callbacks->reloc_overflow)
+ (r->info, NULL, r->name, r->howto->name, (bfd_vma) 0,
+ input_bfd, r->input_section, r->reloc->r_offset));
+ return TRUE;
+ }
+
+ perform_relocation (r->howto, r->reloc, entry->value, r->input_section,
+ input_bfd, r->contents);
+ }
+
+ return TRUE;
+}
+
+/* Relocate a RISC-V ELF section.
+
+ The RELOCATE_SECTION function is called by the new ELF backend linker
+ to handle the relocations for a section.
+
+ The relocs are always passed as Rela structures.
+
+ This function is responsible for adjusting the section contents as
+ necessary, and (if generating a relocatable output file) adjusting
+ the reloc addend as necessary.
+
+ This function does not have to worry about setting the reloc
+ address or the reloc symbol index.
+
+ LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+ LOCAL_SECTIONS is an array giving the section in the input file
+ corresponding to the st_shndx field of each local symbol.
+
+ The global hash table entry for the global symbols can be found
+ via elf_sym_hashes (input_bfd).
+
+ When generating relocatable output, this function must handle
+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is
+ going to be the section symbol corresponding to the output
+ section, which means that the addend must be adjusted
+ accordingly. */
+
+static bfd_boolean
+riscv_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+ bfd *input_bfd, asection *input_section,
+ bfd_byte *contents, Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ Elf_Internal_Rela *rel;
+ Elf_Internal_Rela *relend;
+ riscv_pcrel_relocs pcrel_relocs;
+ bfd_boolean ret = FALSE;
+ asection *sreloc = elf_section_data (input_section)->sreloc;
+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (input_bfd);
+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
+ bfd_vma *local_got_offsets = elf_local_got_offsets (input_bfd);
+
+ if (!riscv_init_pcrel_relocs (&pcrel_relocs))
+ return FALSE;
+
+ relend = relocs + input_section->reloc_count;
+ for (rel = relocs; rel < relend; rel++)
+ {
+ unsigned long r_symndx;
+ struct elf_link_hash_entry *h;
+ Elf_Internal_Sym *sym;
+ asection *sec;
+ bfd_vma relocation;
+ bfd_reloc_status_type r = bfd_reloc_ok;
+ const char *name;
+ bfd_vma off, ie_off;
+ bfd_boolean unresolved_reloc, is_ie = FALSE;
+ bfd_vma pc = sec_addr (input_section) + rel->r_offset;
+ int r_type = ELFNN_R_TYPE (rel->r_info), tls_type;
+ reloc_howto_type *howto = riscv_elf_rtype_to_howto (r_type);
+ const char *msg = NULL;
+
+ if (r_type == R_RISCV_GNU_VTINHERIT || r_type == R_RISCV_GNU_VTENTRY)
+ continue;
+
+ /* This is a final link. */
+ r_symndx = ELFNN_R_SYM (rel->r_info);
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+ unresolved_reloc = FALSE;
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections[r_symndx];
+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+ }
+ else
+ {
+ bfd_boolean warned, ignored;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes,
+ h, sec, relocation,
+ unresolved_reloc, warned, ignored);
+ if (warned)
+ {
+ /* To avoid generating warning messages about truncated
+ relocations, set the relocation's address to be the same as
+ the start of this section. */
+ if (input_section->output_section != NULL)
+ relocation = input_section->output_section->vma;
+ else
+ relocation = 0;
+ }
+ }
+
+ if (sec != NULL && discarded_section (sec))
+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
+ rel, 1, relend, howto, 0, contents);
+
+ if (bfd_link_relocatable (info))
+ continue;
+
+ if (h != NULL)
+ name = h->root.root.string;
+ else
+ {
+ name = (bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name));
+ if (name == NULL || *name == '\0')
+ name = bfd_section_name (input_bfd, sec);
+ }
+
+ switch (r_type)
+ {
+ case R_RISCV_NONE:
+ case R_RISCV_TPREL_ADD:
+ case R_RISCV_COPY:
+ case R_RISCV_JUMP_SLOT:
+ case R_RISCV_RELATIVE:
+ /* These require nothing of us at all. */
+ continue;
+
+ case R_RISCV_HI20:
+ case R_RISCV_BRANCH:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_LUI:
+ case R_RISCV_LO12_I:
+ case R_RISCV_LO12_S:
+ /* These require no special handling beyond perform_relocation. */
+ break;
+
+ case R_RISCV_GOT_HI20:
+ if (h != NULL)
+ {
+ bfd_boolean dyn, pic;
+
+ off = h->got.offset;
+ BFD_ASSERT (off != (bfd_vma) -1);
+ dyn = elf_hash_table (info)->dynamic_sections_created;
+ pic = bfd_link_pic (info);
+
+ if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, pic, h)
+ || (pic && SYMBOL_REFERENCES_LOCAL (info, h)))
+ {
+ /* This is actually a static link, or it is a
+ -Bsymbolic link and the symbol is defined
+ locally, or the symbol was forced to be local
+ because of a version file. We must initialize
+ this entry in the global offset table. Since the
+ offset must always be a multiple of the word size,
+ we use the least significant bit to record whether
+ we have initialized it already.
+
+ When doing a dynamic link, we create a .rela.got
+ relocation entry to initialize the value. This
+ is done in the finish_dynamic_symbol routine. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ bfd_put_NN (output_bfd, relocation,
+ htab->elf.sgot->contents + off);
+ h->got.offset |= 1;
+ }
+ }
+ else
+ unresolved_reloc = FALSE;
+ }
+ else
+ {
+ BFD_ASSERT (local_got_offsets != NULL
+ && local_got_offsets[r_symndx] != (bfd_vma) -1);
+
+ off = local_got_offsets[r_symndx];
+
+ /* The offset must always be a multiple of the word size.
+ So, we can use the least significant bit to record
+ whether we have already processed this entry. */
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ if (bfd_link_pic (info))
+ {
+ asection *s;
+ Elf_Internal_Rela outrel;
+
+ /* We need to generate a R_RISCV_RELATIVE reloc
+ for the dynamic linker. */
+ s = htab->elf.srelgot;
+ BFD_ASSERT (s != NULL);
+
+ outrel.r_offset = sec_addr (htab->elf.sgot) + off;
+ outrel.r_info =
+ ELFNN_R_INFO (0, R_RISCV_RELATIVE);
+ outrel.r_addend = relocation;
+ relocation = 0;
+ riscv_elf_append_rela (output_bfd, s, &outrel);
+ }
+
+ bfd_put_NN (output_bfd, relocation,
+ htab->elf.sgot->contents + off);
+ local_got_offsets[r_symndx] |= 1;
+ }
+ }
+ relocation = sec_addr (htab->elf.sgot) + off;
+ if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, relocation))
+ r = bfd_reloc_overflow;
+ break;
+
+ case R_RISCV_ADD8:
+ case R_RISCV_ADD16:
+ case R_RISCV_ADD32:
+ case R_RISCV_ADD64:
+ {
+ bfd_vma old_value = bfd_get (howto->bitsize, input_bfd,
+ contents + rel->r_offset);
+ relocation = old_value + relocation;
+ }
+ break;
+
+ case R_RISCV_SUB8:
+ case R_RISCV_SUB16:
+ case R_RISCV_SUB32:
+ case R_RISCV_SUB64:
+ {
+ bfd_vma old_value = bfd_get (howto->bitsize, input_bfd,
+ contents + rel->r_offset);
+ relocation = old_value - relocation;
+ }
+ break;
+
+ case R_RISCV_CALL_PLT:
+ case R_RISCV_CALL:
+ case R_RISCV_JAL:
+ case R_RISCV_RVC_JUMP:
+ if (bfd_link_pic (info) && h != NULL && h->plt.offset != MINUS_ONE)
+ {
+ /* Refer to the PLT entry. */
+ relocation = sec_addr (htab->elf.splt) + h->plt.offset;
+ unresolved_reloc = FALSE;
+ }
+ break;
+
+ case R_RISCV_TPREL_HI20:
+ relocation = tpoff (info, relocation);
+ break;
+
+ case R_RISCV_TPREL_LO12_I:
+ case R_RISCV_TPREL_LO12_S:
+ relocation = tpoff (info, relocation);
+ if (VALID_ITYPE_IMM (relocation + rel->r_addend))
+ {
+ /* We can use tp as the base register. */
+ bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+ insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
+ insn |= X_TP << OP_SH_RS1;
+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+ }
+ break;
+
+ case R_RISCV_GPREL_I:
+ case R_RISCV_GPREL_S:
+ {
+ bfd_vma gp = riscv_global_pointer_value (info);
+ bfd_boolean x0_base = VALID_ITYPE_IMM (relocation + rel->r_addend);
+ if (x0_base || VALID_ITYPE_IMM (relocation + rel->r_addend - gp))
+ {
+ /* We can use x0 or gp as the base register. */
+ bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+ insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
+ if (!x0_base)
+ {
+ rel->r_addend -= gp;
+ insn |= X_GP << OP_SH_RS1;
+ }
+ bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+ }
+ else
+ r = bfd_reloc_overflow;
+ break;
+ }
+
+ case R_RISCV_PCREL_HI20:
+ if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc,
+ relocation + rel->r_addend))
+ r = bfd_reloc_overflow;
+ break;
+
+ case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_PCREL_LO12_S:
+ if (riscv_record_pcrel_lo_reloc (&pcrel_relocs, input_section, info,
+ howto, rel, relocation, name,
+ contents))
+ continue;
+ r = bfd_reloc_overflow;
+ break;
+
+ case R_RISCV_TLS_DTPREL32:
+ case R_RISCV_TLS_DTPREL64:
+ relocation = dtpoff (info, relocation);
+ break;
+
+ case R_RISCV_32:
+ case R_RISCV_64:
+ if ((input_section->flags & SEC_ALLOC) == 0)
+ break;
+
+ if ((bfd_link_pic (info)
+ && (h == NULL
+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak)
+ && (! howto->pc_relative
+ || !SYMBOL_CALLS_LOCAL (info, h)))
+ || (!bfd_link_pic (info)
+ && h != NULL
+ && h->dynindx != -1
+ && !h->non_got_ref
+ && ((h->def_dynamic
+ && !h->def_regular)
+ || h->root.type == bfd_link_hash_undefweak
+ || h->root.type == bfd_link_hash_undefined)))
+ {
+ Elf_Internal_Rela outrel;
+ bfd_boolean skip_static_relocation, skip_dynamic_relocation;
+
+ /* When generating a shared object, these relocations
+ are copied into the output file to be resolved at run
+ time. */
+
+ outrel.r_offset =
+ _bfd_elf_section_offset (output_bfd, info, input_section,
+ rel->r_offset);
+ skip_static_relocation = outrel.r_offset != (bfd_vma) -2;
+ skip_dynamic_relocation = outrel.r_offset >= (bfd_vma) -2;
+ outrel.r_offset += sec_addr (input_section);
+
+ if (skip_dynamic_relocation)
+ memset (&outrel, 0, sizeof outrel);
+ else if (h != NULL && h->dynindx != -1
+ && !(bfd_link_pic (info)
+ && SYMBOLIC_BIND (info, h)
+ && h->def_regular))
+ {
+ outrel.r_info = ELFNN_R_INFO (h->dynindx, r_type);
+ outrel.r_addend = rel->r_addend;
+ }
+ else
+ {
+ outrel.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE);
+ outrel.r_addend = relocation + rel->r_addend;
+ }
+
+ riscv_elf_append_rela (output_bfd, sreloc, &outrel);
+ if (skip_static_relocation)
+ continue;
+ }
+ break;
+
+ case R_RISCV_TLS_GOT_HI20:
+ is_ie = TRUE;
+ /* Fall through. */
+
+ case R_RISCV_TLS_GD_HI20:
+ if (h != NULL)
+ {
+ off = h->got.offset;
+ h->got.offset |= 1;
+ }
+ else
+ {
+ off = local_got_offsets[r_symndx];
+ local_got_offsets[r_symndx] |= 1;
+ }
+
+ tls_type = _bfd_riscv_elf_tls_type (input_bfd, h, r_symndx);
+ BFD_ASSERT (tls_type & (GOT_TLS_IE | GOT_TLS_GD));
+ /* If this symbol is referenced by both GD and IE TLS, the IE
+ reference's GOT slot follows the GD reference's slots. */
+ ie_off = 0;
+ if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_IE))
+ ie_off = 2 * GOT_ENTRY_SIZE;
+
+ if ((off & 1) != 0)
+ off &= ~1;
+ else
+ {
+ Elf_Internal_Rela outrel;
+ int indx = 0;
+ bfd_boolean need_relocs = FALSE;
+
+ if (htab->elf.srelgot == NULL)
+ abort ();
+
+ if (h != NULL)
+ {
+ bfd_boolean dyn, pic;
+ dyn = htab->elf.dynamic_sections_created;
+ pic = bfd_link_pic (info);
+
+ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, pic, h)
+ && (!pic || !SYMBOL_REFERENCES_LOCAL (info, h)))
+ indx = h->dynindx;
+ }
+
+ /* The GOT entries have not been initialized yet. Do it
+ now, and emit any relocations. */
+ if ((bfd_link_pic (info) || indx != 0)
+ && (h == NULL
+ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+ || h->root.type != bfd_link_hash_undefweak))
+ need_relocs = TRUE;
+
+ if (tls_type & GOT_TLS_GD)
+ {
+ if (need_relocs)
+ {
+ outrel.r_offset = sec_addr (htab->elf.sgot) + off;
+ outrel.r_addend = 0;
+ outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPMODNN);
+ bfd_put_NN (output_bfd, 0,
+ htab->elf.sgot->contents + off);
+ riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+ if (indx == 0)
+ {
+ BFD_ASSERT (! unresolved_reloc);
+ bfd_put_NN (output_bfd,
+ dtpoff (info, relocation),
+ (htab->elf.sgot->contents + off +
+ RISCV_ELF_WORD_BYTES));
+ }
+ else
+ {
+ bfd_put_NN (output_bfd, 0,
+ (htab->elf.sgot->contents + off +
+ RISCV_ELF_WORD_BYTES));
+ outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN);
+ outrel.r_offset += RISCV_ELF_WORD_BYTES;
+ riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+ }
+ }
+ else
+ {
+ /* If we are not emitting relocations for a
+ general dynamic reference, then we must be in a
+ static link or an executable link with the
+ symbol binding locally. Mark it as belonging
+ to module 1, the executable. */
+ bfd_put_NN (output_bfd, 1,
+ htab->elf.sgot->contents + off);
+ bfd_put_NN (output_bfd,
+ dtpoff (info, relocation),
+ (htab->elf.sgot->contents + off +
+ RISCV_ELF_WORD_BYTES));
+ }
+ }
+
+ if (tls_type & GOT_TLS_IE)
+ {
+ if (need_relocs)
+ {
+ bfd_put_NN (output_bfd, 0,
+ htab->elf.sgot->contents + off + ie_off);
+ outrel.r_offset = sec_addr (htab->elf.sgot)
+ + off + ie_off;
+ outrel.r_addend = 0;
+ if (indx == 0)
+ outrel.r_addend = tpoff (info, relocation);
+ outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_TPRELNN);
+ riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+ }
+ else
+ {
+ bfd_put_NN (output_bfd, tpoff (info, relocation),
+ htab->elf.sgot->contents + off + ie_off);
+ }
+ }
+ }
+
+ BFD_ASSERT (off < (bfd_vma) -2);
+ relocation = sec_addr (htab->elf.sgot) + off + (is_ie ? ie_off : 0);
+ if (!riscv_record_pcrel_hi_reloc (&pcrel_relocs, pc, relocation))
+ r = bfd_reloc_overflow;
+ unresolved_reloc = FALSE;
+ break;
+
+ default:
+ r = bfd_reloc_notsupported;
+ }
+
+ /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
+ because such sections are not SEC_ALLOC and thus ld.so will
+ not process them. */
+ if (unresolved_reloc
+ && !((input_section->flags & SEC_DEBUGGING) != 0
+ && h->def_dynamic)
+ && _bfd_elf_section_offset (output_bfd, info, input_section,
+ rel->r_offset) != (bfd_vma) -1)
+ {
+ (*_bfd_error_handler)
+ (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
+ input_bfd,
+ input_section,
+ (long) rel->r_offset,
+ howto->name,
+ h->root.root.string);
+ continue;
+ }
+
+ if (r == bfd_reloc_ok)
+ r = perform_relocation (howto, rel, relocation, input_section,
+ input_bfd, contents);
+
+ switch (r)
+ {
+ case bfd_reloc_ok:
+ continue;
+
+ case bfd_reloc_overflow:
+ info->callbacks->reloc_overflow
+ (info, (h ? &h->root : NULL), name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
+ break;
+
+ case bfd_reloc_undefined:
+ info->callbacks->undefined_symbol
+ (info, name, input_bfd, input_section, rel->r_offset,
+ TRUE);
+ break;
+
+ case bfd_reloc_outofrange:
+ msg = _("internal error: out of range error");
+ break;
+
+ case bfd_reloc_notsupported:
+ msg = _("internal error: unsupported relocation error");
+ break;
+
+ case bfd_reloc_dangerous:
+ msg = _("internal error: dangerous relocation");
+ break;
+
+ default:
+ msg = _("internal error: unknown error");
+ break;
+ }
+
+ if (msg)
+ info->callbacks->warning
+ (info, msg, name, input_bfd, input_section, rel->r_offset);
+ goto out;
+ }
+
+ ret = riscv_resolve_pcrel_lo_relocs (&pcrel_relocs);
+out:
+ riscv_free_pcrel_relocs (&pcrel_relocs);
+ return ret;
+}
+
+/* Finish up dynamic symbol handling. We set the contents of various
+ dynamic sections here. */
+
+static bfd_boolean
+riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ Elf_Internal_Sym *sym)
+{
+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+ const struct elf_backend_data *bed = get_elf_backend_data (output_bfd);
+
+ if (h->plt.offset != (bfd_vma) -1)
+ {
+ /* We've decided to create a PLT entry for this symbol. */
+ bfd_byte *loc;
+ bfd_vma i, header_address, plt_idx, got_address;
+ uint32_t plt_entry[PLT_ENTRY_INSNS];
+ Elf_Internal_Rela rela;
+
+ BFD_ASSERT (h->dynindx != -1);
+
+ /* Calculate the address of the PLT header. */
+ header_address = sec_addr (htab->elf.splt);
+
+ /* Calculate the index of the entry. */
+ plt_idx = (h->plt.offset - PLT_HEADER_SIZE) / PLT_ENTRY_SIZE;
+
+ /* Calculate the address of the .got.plt entry. */
+ got_address = riscv_elf_got_plt_val (plt_idx, info);
+
+ /* Find out where the .plt entry should go. */
+ loc = htab->elf.splt->contents + h->plt.offset;
+
+ /* Fill in the PLT entry itself. */
+ riscv_make_plt_entry (got_address, header_address + h->plt.offset,
+ plt_entry);
+ for (i = 0; i < PLT_ENTRY_INSNS; i++)
+ bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i);
+
+ /* Fill in the initial value of the .got.plt entry. */
+ loc = htab->elf.sgotplt->contents
+ + (got_address - sec_addr (htab->elf.sgotplt));
+ bfd_put_NN (output_bfd, sec_addr (htab->elf.splt), loc);
+
+ /* Fill in the entry in the .rela.plt section. */
+ rela.r_offset = got_address;
+ rela.r_addend = 0;
+ rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_JUMP_SLOT);
+
+ loc = htab->elf.srelplt->contents + plt_idx * sizeof (ElfNN_External_Rela);
+ bed->s->swap_reloca_out (output_bfd, &rela, loc);
+
+ if (!h->def_regular)
+ {
+ /* Mark the symbol as undefined, rather than as defined in
+ the .plt section. Leave the value alone. */
+ sym->st_shndx = SHN_UNDEF;
+ /* If the symbol is weak, we do need to clear the value.
+ Otherwise, the PLT entry would provide a definition for
+ the symbol even if the symbol wasn't defined anywhere,
+ and so the symbol would never be NULL. */
+ if (!h->ref_regular_nonweak)
+ sym->st_value = 0;
+ }
+ }
+
+ if (h->got.offset != (bfd_vma) -1
+ && !(riscv_elf_hash_entry(h)->tls_type & (GOT_TLS_GD | GOT_TLS_IE)))
+ {
+ asection *sgot;
+ asection *srela;
+ Elf_Internal_Rela rela;
+
+ /* This symbol has an entry in the GOT. Set it up. */
+
+ sgot = htab->elf.sgot;
+ srela = htab->elf.srelgot;
+ BFD_ASSERT (sgot != NULL && srela != NULL);
+
+ rela.r_offset = sec_addr (sgot) + (h->got.offset &~ (bfd_vma) 1);
+
+ /* If this is a -Bsymbolic link, and the symbol is defined
+ locally, we just want to emit a RELATIVE reloc. Likewise if
+ the symbol was forced to be local because of a version file.
+ The entry in the global offset table will already have been
+ initialized in the relocate_section function. */
+ if (bfd_link_pic (info)
+ && (info->symbolic || h->dynindx == -1)
+ && h->def_regular)
+ {
+ asection *sec = h->root.u.def.section;
+ rela.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE);
+ rela.r_addend = (h->root.u.def.value
+ + sec->output_section->vma
+ + sec->output_offset);
+ }
+ else
+ {
+ BFD_ASSERT (h->dynindx != -1);
+ rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_NN);
+ rela.r_addend = 0;
+ }
+
+ bfd_put_NN (output_bfd, 0,
+ sgot->contents + (h->got.offset & ~(bfd_vma) 1));
+ riscv_elf_append_rela (output_bfd, srela, &rela);
+ }
+
+ if (h->needs_copy)
+ {
+ Elf_Internal_Rela rela;
+
+ /* This symbols needs a copy reloc. Set it up. */
+ BFD_ASSERT (h->dynindx != -1);
+
+ rela.r_offset = sec_addr (h->root.u.def.section) + h->root.u.def.value;
+ rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_COPY);
+ rela.r_addend = 0;
+ riscv_elf_append_rela (output_bfd, htab->srelbss, &rela);
+ }
+
+ /* Mark some specially defined symbols as absolute. */
+ if (h == htab->elf.hdynamic
+ || (h == htab->elf.hgot || h == htab->elf.hplt))
+ sym->st_shndx = SHN_ABS;
+
+ return TRUE;
+}
+
+/* Finish up the dynamic sections. */
+
+static bfd_boolean
+riscv_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
+ bfd *dynobj, asection *sdyn)
+{
+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+ const struct elf_backend_data *bed = get_elf_backend_data (output_bfd);
+ size_t dynsize = bed->s->sizeof_dyn;
+ bfd_byte *dyncon, *dynconend;
+
+ dynconend = sdyn->contents + sdyn->size;
+ for (dyncon = sdyn->contents; dyncon < dynconend; dyncon += dynsize)
+ {
+ Elf_Internal_Dyn dyn;
+ asection *s;
+
+ bed->s->swap_dyn_in (dynobj, dyncon, &dyn);
+
+ switch (dyn.d_tag)
+ {
+ case DT_PLTGOT:
+ s = htab->elf.sgotplt;
+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
+ break;
+ case DT_JMPREL:
+ s = htab->elf.srelplt;
+ dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
+ break;
+ case DT_PLTRELSZ:
+ s = htab->elf.srelplt;
+ dyn.d_un.d_val = s->size;
+ break;
+ default:
+ continue;
+ }
+
+ bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+ }
+ return TRUE;
+}
+
+static bfd_boolean
+riscv_elf_finish_dynamic_sections (bfd *output_bfd,
+ struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ asection *sdyn;
+ struct riscv_elf_link_hash_table *htab;
+
+ htab = riscv_elf_hash_table (info);
+ BFD_ASSERT (htab != NULL);
+ dynobj = htab->elf.dynobj;
+
+ sdyn = bfd_get_linker_section (dynobj, ".dynamic");
+
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ asection *splt;
+ bfd_boolean ret;
+
+ splt = htab->elf.splt;
+ BFD_ASSERT (splt != NULL && sdyn != NULL);
+
+ ret = riscv_finish_dyn (output_bfd, info, dynobj, sdyn);
+
+ if (ret != TRUE)
+ return ret;
+
+ /* Fill in the head and tail entries in the procedure linkage table. */
+ if (splt->size > 0)
+ {
+ int i;
+ uint32_t plt_header[PLT_HEADER_INSNS];
+ riscv_make_plt_header (sec_addr (htab->elf.sgotplt),
+ sec_addr (splt), plt_header);
+
+ for (i = 0; i < PLT_HEADER_INSNS; i++)
+ bfd_put_32 (output_bfd, plt_header[i], splt->contents + 4*i);
+ }
+
+ elf_section_data (splt->output_section)->this_hdr.sh_entsize
+ = PLT_ENTRY_SIZE;
+ }
+
+ if (htab->elf.sgotplt)
+ {
+ asection *output_section = htab->elf.sgotplt->output_section;
+
+ if (bfd_is_abs_section (output_section))
+ {
+ (*_bfd_error_handler)
+ (_("discarded output section: `%A'"), htab->elf.sgotplt);
+ return FALSE;
+ }
+
+ if (htab->elf.sgotplt->size > 0)
+ {
+ /* Write the first two entries in .got.plt, needed for the dynamic
+ linker. */
+ bfd_put_NN (output_bfd, (bfd_vma) -1, htab->elf.sgotplt->contents);
+ bfd_put_NN (output_bfd, (bfd_vma) 0,
+ htab->elf.sgotplt->contents + GOT_ENTRY_SIZE);
+ }
+
+ elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
+ }
+
+ if (htab->elf.sgot)
+ {
+ asection *output_section = htab->elf.sgot->output_section;
+
+ if (htab->elf.sgot->size > 0)
+ {
+ /* Set the first entry in the global offset table to the address of
+ the dynamic section. */
+ bfd_vma val = sdyn ? sec_addr (sdyn) : 0;
+ bfd_put_NN (output_bfd, val, htab->elf.sgot->contents);
+ }
+
+ elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
+ }
+
+ return TRUE;
+}
+
+/* Return address for Ith PLT stub in section PLT, for relocation REL
+ or (bfd_vma) -1 if it should not be included. */
+
+static bfd_vma
+riscv_elf_plt_sym_val (bfd_vma i, const asection *plt,
+ const arelent *rel ATTRIBUTE_UNUSED)
+{
+ return plt->vma + PLT_HEADER_SIZE + i * PLT_ENTRY_SIZE;
+}
+
+static enum elf_reloc_type_class
+riscv_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
+ const asection *rel_sec ATTRIBUTE_UNUSED,
+ const Elf_Internal_Rela *rela)
+{
+ switch (ELFNN_R_TYPE (rela->r_info))
+ {
+ case R_RISCV_RELATIVE:
+ return reloc_class_relative;
+ case R_RISCV_JUMP_SLOT:
+ return reloc_class_plt;
+ case R_RISCV_COPY:
+ return reloc_class_copy;
+ default:
+ return reloc_class_normal;
+ }
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+
+static bfd_boolean
+_bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
+{
+ flagword new_flags = elf_elfheader (ibfd)->e_flags;
+ flagword old_flags = elf_elfheader (obfd)->e_flags;
+
+ if (!is_riscv_elf (ibfd) || !is_riscv_elf (obfd))
+ return TRUE;
+
+ if (strcmp (bfd_get_target (ibfd), bfd_get_target (obfd)) != 0)
+ {
+ (*_bfd_error_handler)
+ (_("%B: ABI is incompatible with that of the selected emulation"),
+ ibfd);
+ return FALSE;
+ }
+
+ if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
+ return FALSE;
+
+ if (! elf_flags_init (obfd))
+ {
+ elf_flags_init (obfd) = TRUE;
+ elf_elfheader (obfd)->e_flags = new_flags;
+ return TRUE;
+ }
+
+ /* Disallow linking soft-float and hard-float. */
+ if ((old_flags ^ new_flags) & EF_RISCV_SOFT_FLOAT)
+ {
+ (*_bfd_error_handler)
+ (_("%B: can't link hard-float modules with soft-float modules"), ibfd);
+ goto fail;
+ }
+
+ /* Allow linking RVC and non-RVC, and keep the RVC flag. */
+ elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC;
+
+ return TRUE;
+
+fail:
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+}
+
+/* Delete some bytes from a section while relaxing. */
+
+static bfd_boolean
+riscv_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, size_t count)
+{
+ unsigned int i, symcount;
+ bfd_vma toaddr = sec->size;
+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd);
+ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ unsigned int sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
+ struct bfd_elf_section_data *data = elf_section_data (sec);
+ bfd_byte *contents = data->this_hdr.contents;
+
+ /* Actually delete the bytes. */
+ sec->size -= count;
+ memmove (contents + addr, contents + addr + count, toaddr - addr - count);
+
+ /* Adjust the location of all of the relocs. Note that we need not
+ adjust the addends, since all PC-relative references must be against
+ symbols, which we will adjust below. */
+ for (i = 0; i < sec->reloc_count; i++)
+ if (data->relocs[i].r_offset > addr && data->relocs[i].r_offset < toaddr)
+ data->relocs[i].r_offset -= count;
+
+ /* Adjust the local symbols defined in this section. */
+ for (i = 0; i < symtab_hdr->sh_info; i++)
+ {
+ Elf_Internal_Sym *sym = (Elf_Internal_Sym *) symtab_hdr->contents + i;
+ if (sym->st_shndx == sec_shndx)
+ {
+ /* If the symbol is in the range of memory we just moved, we
+ have to adjust its value. */
+ if (sym->st_value > addr && sym->st_value <= toaddr)
+ sym->st_value -= count;
+
+ /* If the symbol *spans* the bytes we just deleted (i.e. its
+ *end* is in the moved bytes but its *start* isn't), then we
+ must adjust its size. */
+ if (sym->st_value <= addr
+ && sym->st_value + sym->st_size > addr
+ && sym->st_value + sym->st_size <= toaddr)
+ sym->st_size -= count;
+ }
+ }
+
+ /* Now adjust the global symbols defined in this section. */
+ symcount = ((symtab_hdr->sh_size / sizeof (ElfNN_External_Sym))
+ - symtab_hdr->sh_info);
+
+ for (i = 0; i < symcount; i++)
+ {
+ struct elf_link_hash_entry *sym_hash = sym_hashes[i];
+
+ if ((sym_hash->root.type == bfd_link_hash_defined
+ || sym_hash->root.type == bfd_link_hash_defweak)
+ && sym_hash->root.u.def.section == sec)
+ {
+ /* As above, adjust the value if needed. */
+ if (sym_hash->root.u.def.value > addr
+ && sym_hash->root.u.def.value <= toaddr)
+ sym_hash->root.u.def.value -= count;
+
+ /* As above, adjust the size if needed. */
+ if (sym_hash->root.u.def.value <= addr
+ && sym_hash->root.u.def.value + sym_hash->size > addr
+ && sym_hash->root.u.def.value + sym_hash->size <= toaddr)
+ sym_hash->size -= count;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Relax AUIPC + JALR into JAL. */
+
+static bfd_boolean
+_bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
+ struct bfd_link_info *link_info,
+ Elf_Internal_Rela *rel,
+ bfd_vma symval,
+ unsigned int max_alignment ATTRIBUTE_UNUSED,
+ bfd_boolean *again)
+{
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ bfd_signed_vma foff = symval - (sec_addr (sec) + rel->r_offset);
+ bfd_boolean near_zero = (symval + RISCV_IMM_REACH/2) < RISCV_IMM_REACH;
+ bfd_vma auipc, jalr;
+ int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+
+ /* If the call crosses section boundaries, an alignment directive could
+ cause the PC-relative offset to later increase. Assume at most
+ page-alignment, and account for this by adding some slop. */
+ if (VALID_UJTYPE_IMM (foff) && sym_sec->output_section != sec->output_section)
+ foff += (foff < 0 ? -ELF_MAXPAGESIZE : ELF_MAXPAGESIZE);
+
+ /* See if this function call can be shortened. */
+ if (!VALID_UJTYPE_IMM (foff) && !(!bfd_link_pic (link_info) && near_zero))
+ return TRUE;
+
+ /* Shorten the function call. */
+ BFD_ASSERT (rel->r_offset + 8 <= sec->size);
+
+ auipc = bfd_get_32 (abfd, contents + rel->r_offset);
+ jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
+ rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
+ rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32;
+
+ if (rvc && (rd == 0 || rd == X_RA))
+ {
+ /* Relax to C.J[AL] rd, addr. */
+ r_type = R_RISCV_RVC_JUMP;
+ auipc = rd == 0 ? MATCH_C_J : MATCH_C_JAL;
+ len = 2;
+ }
+ else if (VALID_UJTYPE_IMM (foff))
+ {
+ /* Relax to JAL rd, addr. */
+ r_type = R_RISCV_JAL;
+ auipc = MATCH_JAL | (rd << OP_SH_RD);
+ }
+ else /* near_zero */
+ {
+ /* Relax to JALR rd, x0, addr. */
+ r_type = R_RISCV_LO12_I;
+ auipc = MATCH_JALR | (rd << OP_SH_RD);
+ }
+
+ /* Replace the R_RISCV_CALL reloc. */
+ rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), r_type);
+ /* Replace the AUIPC. */
+ bfd_put (8 * len, abfd, auipc, contents + rel->r_offset);
+
+ /* Delete unnecessary JALR. */
+ *again = TRUE;
+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + len, 8 - len);
+}
+
+/* Traverse all output sections and return the max alignment. */
+
+static unsigned int
+_bfd_riscv_get_max_alignment (asection *sec)
+{
+ unsigned int max_alignment_power = 0;
+ asection *o;
+
+ for (o = sec->output_section->owner->sections; o != NULL; o = o->next)
+ {
+ if (o->alignment_power > max_alignment_power)
+ max_alignment_power = o->alignment_power;
+ }
+
+ return 1 << max_alignment_power;
+}
+
+/* Relax non-PIC global variable references. */
+
+static bfd_boolean
+_bfd_riscv_relax_lui (bfd *abfd, asection *sec, asection *sym_sec,
+ struct bfd_link_info *link_info,
+ Elf_Internal_Rela *rel,
+ bfd_vma symval,
+ unsigned int max_alignment,
+ bfd_boolean *again)
+{
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ bfd_vma gp = riscv_global_pointer_value (link_info);
+ int use_rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+
+ /* Mergeable symbols and code might later move out of range. */
+ if (sym_sec->flags & (SEC_MERGE | SEC_CODE))
+ return TRUE;
+
+ BFD_ASSERT (rel->r_offset + 4 <= sec->size);
+
+ /* Is the reference in range of x0 or gp?
+ Valid gp range conservatively because of alignment issue. */
+ if (VALID_ITYPE_IMM (symval)
+ || (symval >= gp && VALID_ITYPE_IMM (symval - gp + max_alignment))
+ || (symval < gp && VALID_ITYPE_IMM (symval - gp - max_alignment)))
+ {
+ unsigned sym = ELFNN_R_SYM (rel->r_info);
+ switch (ELFNN_R_TYPE (rel->r_info))
+ {
+ case R_RISCV_LO12_I:
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
+ return TRUE;
+
+ case R_RISCV_LO12_S:
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
+ return TRUE;
+
+ case R_RISCV_HI20:
+ /* We can delete the unnecessary LUI and reloc. */
+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+ *again = TRUE;
+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4);
+
+ default:
+ abort ();
+ }
+ }
+
+ /* Can we relax LUI to C.LUI? Alignment might move the section forward;
+ account for this assuming page alignment at worst. */
+ if (use_rvc
+ && ELFNN_R_TYPE (rel->r_info) == R_RISCV_HI20
+ && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
+ && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE)))
+ {
+ /* Replace LUI with C.LUI if legal (i.e., rd != x2/sp). */
+ bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
+ if (((lui >> OP_SH_RD) & OP_MASK_RD) == X_SP)
+ return TRUE;
+
+ lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI;
+ bfd_put_32 (abfd, lui, contents + rel->r_offset);
+
+ /* Replace the R_RISCV_HI20 reloc. */
+ rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_RISCV_RVC_LUI);
+
+ *again = TRUE;
+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2, 2);
+ }
+
+ return TRUE;
+}
+
+/* Relax non-PIC TLS references. */
+
+static bfd_boolean
+_bfd_riscv_relax_tls_le (bfd *abfd, asection *sec,
+ asection *sym_sec ATTRIBUTE_UNUSED,
+ struct bfd_link_info *link_info,
+ Elf_Internal_Rela *rel,
+ bfd_vma symval,
+ unsigned int max_alignment ATTRIBUTE_UNUSED,
+ bfd_boolean *again)
+{
+ /* See if this symbol is in range of tp. */
+ if (RISCV_CONST_HIGH_PART (tpoff (link_info, symval)) != 0)
+ return TRUE;
+
+ /* We can delete the unnecessary LUI and tp add. The LO12 reloc will be
+ made directly tp-relative. */
+ BFD_ASSERT (rel->r_offset + 4 <= sec->size);
+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+
+ *again = TRUE;
+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4);
+}
+
+/* Implement R_RISCV_ALIGN by deleting excess alignment NOPs. */
+
+static bfd_boolean
+_bfd_riscv_relax_align (bfd *abfd, asection *sec,
+ asection *sym_sec ATTRIBUTE_UNUSED,
+ struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
+ Elf_Internal_Rela *rel,
+ bfd_vma symval,
+ unsigned int max_alignment ATTRIBUTE_UNUSED,
+ bfd_boolean *again ATTRIBUTE_UNUSED)
+{
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ bfd_vma alignment = 1, pos;
+ while (alignment <= rel->r_addend)
+ alignment *= 2;
+
+ symval -= rel->r_addend;
+ bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment;
+ bfd_vma nop_bytes = aligned_addr - symval;
+
+ /* Once we've handled an R_RISCV_ALIGN, we can't relax anything else. */
+ sec->sec_flg0 = TRUE;
+
+ /* Make sure there are enough NOPs to actually achieve the alignment. */
+ if (rel->r_addend < nop_bytes)
+ return FALSE;
+
+ /* Delete the reloc. */
+ rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+
+ /* If the number of NOPs is already correct, there's nothing to do. */
+ if (nop_bytes == rel->r_addend)
+ return TRUE;
+
+ /* Write as many RISC-V NOPs as we need. */
+ for (pos = 0; pos < (nop_bytes & -4); pos += 4)
+ bfd_put_32 (abfd, RISCV_NOP, contents + rel->r_offset + pos);
+
+ /* Write a final RVC NOP if need be. */
+ if (nop_bytes % 4 != 0)
+ bfd_put_16 (abfd, RVC_NOP, contents + rel->r_offset + pos);
+
+ /* Delete the excess bytes. */
+ return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes,
+ rel->r_addend - nop_bytes);
+}
+
+/* Relax a section. Pass 0 shortens code sequences unless disabled.
+ Pass 1, which cannot be disabled, handles code alignment directives. */
+
+static bfd_boolean
+_bfd_riscv_relax_section (bfd *abfd, asection *sec,
+ struct bfd_link_info *info, bfd_boolean *again)
+{
+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd);
+ struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+ struct bfd_elf_section_data *data = elf_section_data (sec);
+ Elf_Internal_Rela *relocs;
+ bfd_boolean ret = FALSE;
+ unsigned int i;
+ unsigned int max_alignment;
+
+ *again = FALSE;
+
+ if (bfd_link_relocatable (info)
+ || sec->sec_flg0
+ || (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
+ || (info->disable_target_specific_optimizations
+ && info->relax_pass == 0))
+ return TRUE;
+
+ /* Read this BFD's relocs if we haven't done so already. */
+ if (data->relocs)
+ relocs = data->relocs;
+ else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL,
+ info->keep_memory)))
+ goto fail;
+
+ max_alignment = _bfd_riscv_get_max_alignment (sec);
+
+ /* Examine and consider relaxing each reloc. */
+ for (i = 0; i < sec->reloc_count; i++)
+ {
+ asection *sym_sec;
+ Elf_Internal_Rela *rel = relocs + i;
+ typeof (&_bfd_riscv_relax_call) relax_func = NULL;
+ int type = ELFNN_R_TYPE (rel->r_info);
+ bfd_vma symval;
+
+ if (info->relax_pass == 0)
+ {
+ if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT)
+ relax_func = _bfd_riscv_relax_call;
+ else if (type == R_RISCV_HI20
+ || type == R_RISCV_LO12_I
+ || type == R_RISCV_LO12_S)
+ relax_func = _bfd_riscv_relax_lui;
+ else if (type == R_RISCV_TPREL_HI20 || type == R_RISCV_TPREL_ADD)
+ relax_func = _bfd_riscv_relax_tls_le;
+ }
+ else if (type == R_RISCV_ALIGN)
+ relax_func = _bfd_riscv_relax_align;
+
+ if (!relax_func)
+ continue;
+
+ data->relocs = relocs;
+
+ /* Read this BFD's contents if we haven't done so already. */
+ if (!data->this_hdr.contents
+ && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents))
+ goto fail;
+
+ /* Read this BFD's symbols if we haven't done so already. */
+ if (symtab_hdr->sh_info != 0
+ && !symtab_hdr->contents
+ && !(symtab_hdr->contents =
+ (unsigned char *) bfd_elf_get_elf_syms (abfd, symtab_hdr,
+ symtab_hdr->sh_info,
+ 0, NULL, NULL, NULL)))
+ goto fail;
+
+ /* Get the value of the symbol referred to by the reloc. */
+ if (ELFNN_R_SYM (rel->r_info) < symtab_hdr->sh_info)
+ {
+ /* A local symbol. */
+ Elf_Internal_Sym *isym = ((Elf_Internal_Sym *) symtab_hdr->contents
+ + ELFNN_R_SYM (rel->r_info));
+
+ if (isym->st_shndx == SHN_UNDEF)
+ sym_sec = sec, symval = sec_addr (sec) + rel->r_offset;
+ else
+ {
+ BFD_ASSERT (isym->st_shndx < elf_numsections (abfd));
+ sym_sec = elf_elfsections (abfd)[isym->st_shndx]->bfd_section;
+ if (sec_addr (sym_sec) == 0)
+ continue;
+ symval = sec_addr (sym_sec) + isym->st_value;
+ }
+ }
+ else
+ {
+ unsigned long indx;
+ struct elf_link_hash_entry *h;
+
+ indx = ELFNN_R_SYM (rel->r_info) - symtab_hdr->sh_info;
+ h = elf_sym_hashes (abfd)[indx];
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ if (h->plt.offset != MINUS_ONE)
+ symval = sec_addr (htab->elf.splt) + h->plt.offset;
+ else if (h->root.u.def.section->output_section == NULL
+ || (h->root.type != bfd_link_hash_defined
+ && h->root.type != bfd_link_hash_defweak))
+ continue;
+ else
+ symval = sec_addr (h->root.u.def.section) + h->root.u.def.value;
+
+ sym_sec = h->root.u.def.section;
+ }
+
+ symval += rel->r_addend;
+
+ if (!relax_func (abfd, sec, sym_sec, info, rel, symval,
+ max_alignment, again))
+ goto fail;
+ }
+
+ ret = TRUE;
+
+fail:
+ if (relocs != data->relocs)
+ free (relocs);
+
+ return ret;
+}
+
+#if ARCH_SIZE == 32
+# define PRSTATUS_SIZE 0 /* FIXME */
+# define PRSTATUS_OFFSET_PR_CURSIG 12
+# define PRSTATUS_OFFSET_PR_PID 24
+# define PRSTATUS_OFFSET_PR_REG 72
+# define ELF_GREGSET_T_SIZE 128
+# define PRPSINFO_SIZE 128
+# define PRPSINFO_OFFSET_PR_PID 16
+# define PRPSINFO_OFFSET_PR_FNAME 32
+# define PRPSINFO_OFFSET_PR_PSARGS 48
+#else
+# define PRSTATUS_SIZE 376
+# define PRSTATUS_OFFSET_PR_CURSIG 12
+# define PRSTATUS_OFFSET_PR_PID 32
+# define PRSTATUS_OFFSET_PR_REG 112
+# define ELF_GREGSET_T_SIZE 256
+# define PRPSINFO_SIZE 136
+# define PRPSINFO_OFFSET_PR_PID 24
+# define PRPSINFO_OFFSET_PR_FNAME 40
+# define PRPSINFO_OFFSET_PR_PSARGS 56
+#endif
+
+/* Support for core dump NOTE sections. */
+
+static bfd_boolean
+riscv_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
+{
+ switch (note->descsz)
+ {
+ default:
+ return FALSE;
+
+ case PRSTATUS_SIZE: /* sizeof(struct elf_prstatus) on Linux/RISC-V. */
+ /* pr_cursig */
+ elf_tdata (abfd)->core->signal
+ = bfd_get_16 (abfd, note->descdata + PRSTATUS_OFFSET_PR_CURSIG);
+
+ /* pr_pid */
+ elf_tdata (abfd)->core->lwpid
+ = bfd_get_32 (abfd, note->descdata + PRSTATUS_OFFSET_PR_PID);
+ break;
+ }
+
+ /* Make a ".reg/999" section. */
+ return _bfd_elfcore_make_pseudosection (abfd, ".reg", ELF_GREGSET_T_SIZE,
+ note->descpos + PRSTATUS_OFFSET_PR_REG);
+}
+
+static bfd_boolean
+riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
+{
+ switch (note->descsz)
+ {
+ default:
+ return FALSE;
+
+ case PRPSINFO_SIZE: /* sizeof(struct elf_prpsinfo) on Linux/RISC-V. */
+ /* pr_pid */
+ elf_tdata (abfd)->core->pid
+ = bfd_get_32 (abfd, note->descdata + PRPSINFO_OFFSET_PR_PID);
+
+ /* pr_fname */
+ elf_tdata (abfd)->core->program = _bfd_elfcore_strndup
+ (abfd, note->descdata + PRPSINFO_OFFSET_PR_FNAME, 16);
+
+ /* pr_psargs */
+ elf_tdata (abfd)->core->command = _bfd_elfcore_strndup
+ (abfd, note->descdata + PRPSINFO_OFFSET_PR_PSARGS, 80);
+ break;
+ }
+
+ /* Note that for some reason, a spurious space is tacked
+ onto the end of the args in some (at least one anyway)
+ implementations, so strip it off if it exists. */
+
+ {
+ char *command = elf_tdata (abfd)->core->command;
+ int n = strlen (command);
+
+ if (0 < n && command[n - 1] == ' ')
+ command[n - 1] = '\0';
+ }
+
+ return TRUE;
+}
+
+
+#define TARGET_LITTLE_SYM riscv_elfNN_vec
+#define TARGET_LITTLE_NAME "elfNN-littleriscv"
+
+#define elf_backend_reloc_type_class riscv_reloc_type_class
+
+#define bfd_elfNN_bfd_reloc_name_lookup riscv_reloc_name_lookup
+#define bfd_elfNN_bfd_link_hash_table_create riscv_elf_link_hash_table_create
+#define bfd_elfNN_bfd_reloc_type_lookup riscv_reloc_type_lookup
+#define bfd_elfNN_bfd_merge_private_bfd_data \
+ _bfd_riscv_elf_merge_private_bfd_data
+
+#define elf_backend_copy_indirect_symbol riscv_elf_copy_indirect_symbol
+#define elf_backend_create_dynamic_sections riscv_elf_create_dynamic_sections
+#define elf_backend_check_relocs riscv_elf_check_relocs
+#define elf_backend_adjust_dynamic_symbol riscv_elf_adjust_dynamic_symbol
+#define elf_backend_size_dynamic_sections riscv_elf_size_dynamic_sections
+#define elf_backend_relocate_section riscv_elf_relocate_section
+#define elf_backend_finish_dynamic_symbol riscv_elf_finish_dynamic_symbol
+#define elf_backend_finish_dynamic_sections riscv_elf_finish_dynamic_sections
+#define elf_backend_gc_mark_hook riscv_elf_gc_mark_hook
+#define elf_backend_gc_sweep_hook riscv_elf_gc_sweep_hook
+#define elf_backend_plt_sym_val riscv_elf_plt_sym_val
+#define elf_backend_grok_prstatus riscv_elf_grok_prstatus
+#define elf_backend_grok_psinfo riscv_elf_grok_psinfo
+#define elf_info_to_howto_rel NULL
+#define elf_info_to_howto riscv_info_to_howto_rela
+#define bfd_elfNN_bfd_relax_section _bfd_riscv_relax_section
+
+#define elf_backend_init_index_section _bfd_elf_init_1_index_section
+
+#define elf_backend_can_gc_sections 1
+#define elf_backend_can_refcount 1
+#define elf_backend_want_got_plt 1
+#define elf_backend_plt_readonly 1
+#define elf_backend_plt_alignment 4
+#define elf_backend_want_plt_sym 1
+#define elf_backend_got_header_size (ARCH_SIZE / 8)
+#define elf_backend_rela_normal 1
+#define elf_backend_default_execstack 0
+
+#include "elfNN-target.h"
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
new file mode 100644
index 0000000..18d2b1d
--- /dev/null
+++ b/bfd/elfxx-riscv.c
@@ -0,0 +1,814 @@
+/* RISC-V-specific support for ELF.
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on TILE-Gx and MIPS targets.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/riscv.h"
+#include "opcode/riscv.h"
+#include "libiberty.h"
+#include "elfxx-riscv.h"
+#include <stdint.h>
+
+#define MINUS_ONE ((bfd_vma)0 - 1)
+
+/* The relocation table used for SHT_RELA sections. */
+
+static reloc_howto_type howto_table[] =
+{
+ /* No relocation. */
+ HOWTO (R_RISCV_NONE, /* type */
+ 0, /* rightshift */
+ 3, /* size */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_NONE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 32 bit relocation. */
+ HOWTO (R_RISCV_32, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_32", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64 bit relocation. */
+ HOWTO (R_RISCV_64, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Relocation against a local symbol in a shared object. */
+ HOWTO (R_RISCV_RELATIVE, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_RELATIVE", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0xffffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_COPY, /* type */
+ 0, /* rightshift */
+ 0, /* this one is variable size */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_COPY", /* name */
+ FALSE, /* partial_inplace */
+ 0x0, /* src_mask */
+ 0x0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_JUMP_SLOT, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_JUMP_SLOT", /* name */
+ FALSE, /* partial_inplace */
+ 0x0, /* src_mask */
+ 0x0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Dynamic TLS relocations. */
+ HOWTO (R_RISCV_TLS_DTPMOD32, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_DTPMOD32", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_TLS_DTPMOD64, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_DTPMOD64", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_TLS_DTPREL32, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_DTPREL32", /* name */
+ TRUE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_TLS_DTPREL64, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_DTPREL64", /* name */
+ TRUE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_TLS_TPREL32, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_TPREL32", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_RISCV_TLS_TPREL64, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_TPREL64", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Reserved for future relocs that the dynamic linker must understand. */
+ EMPTY_HOWTO (12),
+ EMPTY_HOWTO (13),
+ EMPTY_HOWTO (14),
+ EMPTY_HOWTO (15),
+
+ /* 12-bit PC-relative branch offset. */
+ HOWTO (R_RISCV_BRANCH, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_BRANCH", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_SBTYPE_IMM (-1U), /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 20-bit PC-relative jump offset. */
+ HOWTO (R_RISCV_JAL, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper 36
+ bits must match the PC + 4. */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_JAL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UJTYPE_IMM (-1U), /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 32-bit PC-relative function call (AUIPC/JALR). */
+ HOWTO (R_RISCV_CALL, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 64, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_CALL", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U) | ((bfd_vma) ENCODE_ITYPE_IMM (-1U) << 32),
+ /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 32-bit PC-relative function call (AUIPC/JALR). */
+ HOWTO (R_RISCV_CALL_PLT, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 64, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_CALL_PLT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U) | ((bfd_vma) ENCODE_ITYPE_IMM (-1U) << 32),
+ /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* High 20 bits of 32-bit PC-relative GOT access. */
+ HOWTO (R_RISCV_GOT_HI20, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_GOT_HI20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 20 bits of 32-bit PC-relative TLS IE GOT access. */
+ HOWTO (R_RISCV_TLS_GOT_HI20, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_GOT_HI20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 20 bits of 32-bit PC-relative TLS GD GOT reference. */
+ HOWTO (R_RISCV_TLS_GD_HI20, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_GD_HI20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 20 bits of 32-bit PC-relative reference. */
+ HOWTO (R_RISCV_PCREL_HI20, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_PCREL_HI20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U), /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* Low 12 bits of a 32-bit PC-relative load or add. */
+ HOWTO (R_RISCV_PCREL_LO12_I, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_PCREL_LO12_I", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_ITYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 12 bits of a 32-bit PC-relative store. */
+ HOWTO (R_RISCV_PCREL_LO12_S, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_PCREL_LO12_S", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_STYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 20 bits of 32-bit absolute address. */
+ HOWTO (R_RISCV_HI20, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_HI20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 12 bits of 32-bit load or add. */
+ HOWTO (R_RISCV_LO12_I, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_LO12_I", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_ITYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 12 bits of 32-bit store. */
+ HOWTO (R_RISCV_LO12_S, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_LO12_S", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_STYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 20 bits of TLS LE thread pointer offset. */
+ HOWTO (R_RISCV_TPREL_HI20, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TPREL_HI20", /* name */
+ TRUE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_UTYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 12 bits of TLS LE thread pointer offset for loads and adds. */
+ HOWTO (R_RISCV_TPREL_LO12_I, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TPREL_LO12_I", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_ITYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Low 12 bits of TLS LE thread pointer offset for stores. */
+ HOWTO (R_RISCV_TPREL_LO12_S, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TPREL_LO12_S", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_STYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* TLS LE thread pointer usage. */
+ HOWTO (R_RISCV_TPREL_ADD, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TPREL_ADD", /* name */
+ TRUE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 8-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_ADD8, /* type */
+ 0, /* rightshift */
+ 0, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_ADD8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 16-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_ADD16, /* type */
+ 0, /* rightshift */
+ 1, /* size */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_ADD16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 32-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_ADD32, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_ADD32", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_ADD64, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_ADD64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 8-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_SUB8, /* type */
+ 0, /* rightshift */
+ 0, /* size */
+ 8, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_SUB8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 16-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_SUB16, /* type */
+ 0, /* rightshift */
+ 1, /* size */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_SUB16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 32-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_SUB32, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_SUB32", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* 64-bit in-place addition, for local label subtraction. */
+ HOWTO (R_RISCV_SUB64, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 64, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_SUB64", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GNU extension to record C++ vtable hierarchy */
+ HOWTO (R_RISCV_GNU_VTINHERIT, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ NULL, /* special_function */
+ "R_RISCV_GNU_VTINHERIT", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* GNU extension to record C++ vtable member usage */
+ HOWTO (R_RISCV_GNU_VTENTRY, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_elf_rel_vtable_reloc_fn, /* special_function */
+ "R_RISCV_GNU_VTENTRY", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* Indicates an alignment statement. The addend field encodes how many
+ bytes of NOPs follow the statement. The desired alignment is the
+ addend rounded up to the next power of two. */
+ HOWTO (R_RISCV_ALIGN, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 0, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_ALIGN", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0, /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 8-bit PC-relative branch offset. */
+ HOWTO (R_RISCV_RVC_BRANCH, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_RVC_BRANCH", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_RVC_B_IMM (-1U), /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* 11-bit PC-relative jump offset. */
+ HOWTO (R_RISCV_RVC_JUMP, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ TRUE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper 36
+ bits must match the PC + 4. */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_RVC_JUMP", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_RVC_J_IMM (-1U), /* dst_mask */
+ TRUE), /* pcrel_offset */
+
+ /* High 6 bits of 18-bit absolute address. */
+ HOWTO (R_RISCV_RVC_LUI, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_RVC_LUI", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_RVC_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 12 bits of 32-bit load or add. */
+ HOWTO (R_RISCV_GPREL_I, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_GPREL_I", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_ITYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* High 12 bits of 32-bit store. */
+ HOWTO (R_RISCV_GPREL_S, /* type */
+ 0, /* rightshift */
+ 2, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_GPREL_S", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ ENCODE_STYPE_IMM (-1U), /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+/* A mapping from BFD reloc types to RISC-V ELF reloc types. */
+
+struct elf_reloc_map {
+ bfd_reloc_code_real_type bfd_val;
+ enum elf_riscv_reloc_type elf_val;
+};
+
+static const struct elf_reloc_map riscv_reloc_map[] =
+{
+ { BFD_RELOC_NONE, R_RISCV_NONE },
+ { BFD_RELOC_32, R_RISCV_32 },
+ { BFD_RELOC_64, R_RISCV_64 },
+ { BFD_RELOC_RISCV_ADD8, R_RISCV_ADD8 },
+ { BFD_RELOC_RISCV_ADD16, R_RISCV_ADD16 },
+ { BFD_RELOC_RISCV_ADD32, R_RISCV_ADD32 },
+ { BFD_RELOC_RISCV_ADD64, R_RISCV_ADD64 },
+ { BFD_RELOC_RISCV_SUB8, R_RISCV_SUB8 },
+ { BFD_RELOC_RISCV_SUB16, R_RISCV_SUB16 },
+ { BFD_RELOC_RISCV_SUB32, R_RISCV_SUB32 },
+ { BFD_RELOC_RISCV_SUB64, R_RISCV_SUB64 },
+ { BFD_RELOC_CTOR, R_RISCV_64 },
+ { BFD_RELOC_12_PCREL, R_RISCV_BRANCH },
+ { BFD_RELOC_RISCV_HI20, R_RISCV_HI20 },
+ { BFD_RELOC_RISCV_LO12_I, R_RISCV_LO12_I },
+ { BFD_RELOC_RISCV_LO12_S, R_RISCV_LO12_S },
+ { BFD_RELOC_RISCV_PCREL_LO12_I, R_RISCV_PCREL_LO12_I },
+ { BFD_RELOC_RISCV_PCREL_LO12_S, R_RISCV_PCREL_LO12_S },
+ { BFD_RELOC_RISCV_CALL, R_RISCV_CALL },
+ { BFD_RELOC_RISCV_CALL_PLT, R_RISCV_CALL_PLT },
+ { BFD_RELOC_RISCV_PCREL_HI20, R_RISCV_PCREL_HI20 },
+ { BFD_RELOC_RISCV_JMP, R_RISCV_JAL },
+ { BFD_RELOC_RISCV_GOT_HI20, R_RISCV_GOT_HI20 },
+ { BFD_RELOC_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD32 },
+ { BFD_RELOC_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL32 },
+ { BFD_RELOC_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPMOD64 },
+ { BFD_RELOC_RISCV_TLS_DTPREL64, R_RISCV_TLS_DTPREL64 },
+ { BFD_RELOC_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL32 },
+ { BFD_RELOC_RISCV_TLS_TPREL64, R_RISCV_TLS_TPREL64 },
+ { BFD_RELOC_RISCV_TPREL_HI20, R_RISCV_TPREL_HI20 },
+ { BFD_RELOC_RISCV_TPREL_ADD, R_RISCV_TPREL_ADD },
+ { BFD_RELOC_RISCV_TPREL_LO12_S, R_RISCV_TPREL_LO12_S },
+ { BFD_RELOC_RISCV_TPREL_LO12_I, R_RISCV_TPREL_LO12_I },
+ { BFD_RELOC_RISCV_TLS_GOT_HI20, R_RISCV_TLS_GOT_HI20 },
+ { BFD_RELOC_RISCV_TLS_GD_HI20, R_RISCV_TLS_GD_HI20 },
+ { BFD_RELOC_RISCV_ALIGN, R_RISCV_ALIGN },
+ { BFD_RELOC_RISCV_RVC_BRANCH, R_RISCV_RVC_BRANCH },
+ { BFD_RELOC_RISCV_RVC_JUMP, R_RISCV_RVC_JUMP },
+ { BFD_RELOC_RISCV_RVC_LUI, R_RISCV_RVC_LUI },
+ { BFD_RELOC_RISCV_GPREL_I, R_RISCV_GPREL_I },
+ { BFD_RELOC_RISCV_GPREL_S, R_RISCV_GPREL_S },
+};
+
+/* Given a BFD reloc type, return a howto structure. */
+
+reloc_howto_type *
+riscv_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (riscv_reloc_map); i++)
+ if (riscv_reloc_map[i].bfd_val == code)
+ return &howto_table[(int) riscv_reloc_map[i].elf_val];
+
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+}
+
+reloc_howto_type *
+riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (howto_table); i++)
+ if (howto_table[i].name && strcasecmp (howto_table[i].name, r_name) == 0)
+ return &howto_table[i];
+
+ return NULL;
+}
+
+reloc_howto_type *
+riscv_elf_rtype_to_howto (unsigned int r_type)
+{
+ if (r_type >= ARRAY_SIZE (howto_table))
+ {
+ (*_bfd_error_handler) (_("unrecognized relocation (0x%x)"), r_type);
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+ }
+ return &howto_table[r_type];
+}
diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
new file mode 100644
index 0000000..9e14150
--- /dev/null
+++ b/bfd/elfxx-riscv.h
@@ -0,0 +1,33 @@
+/* RISC-V ELF specific backend routines.
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on MIPS target.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "elf/common.h"
+#include "elf/internal.h"
+
+extern reloc_howto_type *
+riscv_reloc_name_lookup (bfd *, const char *);
+
+extern reloc_howto_type *
+riscv_reloc_type_lookup (bfd *, bfd_reloc_code_real_type);
+
+extern reloc_howto_type *
+riscv_elf_rtype_to_howto (unsigned int r_type);
diff --git a/include/elf/riscv.h b/include/elf/riscv.h
new file mode 100644
index 0000000..d842876
--- /dev/null
+++ b/include/elf/riscv.h
@@ -0,0 +1,92 @@
+/* RISC-V ELF support for BFD.
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on MIPS ELF support for BFD, by Ian Lance Taylor.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+/* This file holds definitions specific to the RISCV ELF ABI. Note
+ that most of this is not actually implemented by BFD. */
+
+#ifndef _ELF_RISCV_H
+#define _ELF_RISCV_H
+
+#include "elf/reloc-macros.h"
+#include "libiberty.h"
+
+/* Relocation types. */
+START_RELOC_NUMBERS (elf_riscv_reloc_type)
+ /* Relocation types used by the dynamic linker. */
+ RELOC_NUMBER (R_RISCV_NONE, 0)
+ RELOC_NUMBER (R_RISCV_32, 1)
+ RELOC_NUMBER (R_RISCV_64, 2)
+ RELOC_NUMBER (R_RISCV_RELATIVE, 3)
+ RELOC_NUMBER (R_RISCV_COPY, 4)
+ RELOC_NUMBER (R_RISCV_JUMP_SLOT, 5)
+ RELOC_NUMBER (R_RISCV_TLS_DTPMOD32, 6)
+ RELOC_NUMBER (R_RISCV_TLS_DTPMOD64, 7)
+ RELOC_NUMBER (R_RISCV_TLS_DTPREL32, 8)
+ RELOC_NUMBER (R_RISCV_TLS_DTPREL64, 9)
+ RELOC_NUMBER (R_RISCV_TLS_TPREL32, 10)
+ RELOC_NUMBER (R_RISCV_TLS_TPREL64, 11)
+
+ /* Relocation types not used by the dynamic linker. */
+ RELOC_NUMBER (R_RISCV_BRANCH, 16)
+ RELOC_NUMBER (R_RISCV_JAL, 17)
+ RELOC_NUMBER (R_RISCV_CALL, 18)
+ RELOC_NUMBER (R_RISCV_CALL_PLT, 19)
+ RELOC_NUMBER (R_RISCV_GOT_HI20, 20)
+ RELOC_NUMBER (R_RISCV_TLS_GOT_HI20, 21)
+ RELOC_NUMBER (R_RISCV_TLS_GD_HI20, 22)
+ RELOC_NUMBER (R_RISCV_PCREL_HI20, 23)
+ RELOC_NUMBER (R_RISCV_PCREL_LO12_I, 24)
+ RELOC_NUMBER (R_RISCV_PCREL_LO12_S, 25)
+ RELOC_NUMBER (R_RISCV_HI20, 26)
+ RELOC_NUMBER (R_RISCV_LO12_I, 27)
+ RELOC_NUMBER (R_RISCV_LO12_S, 28)
+ RELOC_NUMBER (R_RISCV_TPREL_HI20, 29)
+ RELOC_NUMBER (R_RISCV_TPREL_LO12_I, 30)
+ RELOC_NUMBER (R_RISCV_TPREL_LO12_S, 31)
+ RELOC_NUMBER (R_RISCV_TPREL_ADD, 32)
+ RELOC_NUMBER (R_RISCV_ADD8, 33)
+ RELOC_NUMBER (R_RISCV_ADD16, 34)
+ RELOC_NUMBER (R_RISCV_ADD32, 35)
+ RELOC_NUMBER (R_RISCV_ADD64, 36)
+ RELOC_NUMBER (R_RISCV_SUB8, 37)
+ RELOC_NUMBER (R_RISCV_SUB16, 38)
+ RELOC_NUMBER (R_RISCV_SUB32, 39)
+ RELOC_NUMBER (R_RISCV_SUB64, 40)
+ RELOC_NUMBER (R_RISCV_GNU_VTINHERIT, 41)
+ RELOC_NUMBER (R_RISCV_GNU_VTENTRY, 42)
+ RELOC_NUMBER (R_RISCV_ALIGN, 43)
+ RELOC_NUMBER (R_RISCV_RVC_BRANCH, 44)
+ RELOC_NUMBER (R_RISCV_RVC_JUMP, 45)
+ RELOC_NUMBER (R_RISCV_RVC_LUI, 46)
+ RELOC_NUMBER (R_RISCV_GPREL_I, 47)
+ RELOC_NUMBER (R_RISCV_GPREL_S, 48)
+END_RELOC_NUMBERS (R_RISCV_max)
+
+/* Processor specific flags for the ELF header e_flags field. */
+
+/* File may contain compressed instructions. */
+#define EF_RISCV_RVC 0x0001
+
+/* File uses the soft-float calling convention. */
+#define EF_RISCV_SOFT_FLOAT 0x0002
+
+#endif /* _ELF_RISCV_H */
--
2.7.3
Alan Modra
2016-10-12 00:58:58 UTC
Permalink
Post by Andrew Waterman
+/* Remember all PC-relative high-part relocs we've encountered to help us
+ later resolve the corresponding low-part relocs. */
Why? This sort of thing is usually only needed on REL targets.
Post by Andrew Waterman
+ /* Dynamic TLS relocations. */
+ HOWTO (R_RISCV_TLS_DTPMOD32, /* type */
+ 0, /* rightshift */
+ 4, /* size */
+ 32, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_RISCV_TLS_DTPMOD32", /* name */
+ FALSE, /* partial_inplace */
+ MINUS_ONE, /* src_mask */
+ MINUS_ONE, /* dst_mask */
+ FALSE), /* pcrel_offset */
Here and in a few more howtos you set src_mask non-zero. Again, this
is usually not correct for a RELA target.
--
Alan Modra
Australia Development Lab, IBM
Alan Modra
2016-10-12 01:57:28 UTC
Permalink
Post by Alan Modra
Post by Andrew Waterman
+/* Remember all PC-relative high-part relocs we've encountered to help
us
Post by Andrew Waterman
+ later resolve the corresponding low-part relocs. */
Why? This sort of thing is usually only needed on REL targets.
We'll expound on this comment to explain our strategy. Of course, a simpler
approach might suffice.
It's not a matter of explaining. I think you have something seriously
wrong here. You most likely need to remove all of the hi/lo recording
and use of high value to apply low relocs, or you have a broken ABI.
If the latter then it would pay to fix it sooner rather than later.

The reason hi/lo matching is needed on REL targets is that with the
addend stored in the insn you can only fit a partial addend in an
insn. You need to read both insns and combine the addends to create a
full addend (which is needed to properly perform pc subtraction).
With RELA targets you should have the full addend in the reloc.
--
Alan Modra
Australia Development Lab, IBM
Andrew Waterman
2016-10-12 18:47:26 UTC
Permalink
Post by Alan Modra
Post by Alan Modra
Post by Andrew Waterman
+/* Remember all PC-relative high-part relocs we've encountered to help
us
Post by Andrew Waterman
+ later resolve the corresponding low-part relocs. */
Why? This sort of thing is usually only needed on REL targets.
We'll expound on this comment to explain our strategy. Of course, a simpler
approach might suffice.
It's not a matter of explaining. I think you have something seriously
wrong here. You most likely need to remove all of the hi/lo recording
and use of high value to apply low relocs, or you have a broken ABI.
If the latter then it would pay to fix it sooner rather than later.
The reason hi/lo matching is needed on REL targets is that with the
addend stored in the insn you can only fit a partial addend in an
insn. You need to read both insns and combine the addends to create a
full addend (which is needed to properly perform pc subtraction).
With RELA targets you should have the full addend in the reloc.
It's not that a partial addend is being stored anywhere; it's that
there is a level of indirection. The PC-relative addressing scheme is
relative to the address of the high-part reloc, because of how the ISA
works. So, the value of the low-part reloc depends both on the
address of the high-part reloc and the symbol being referenced. The
alternative would be to put two relocs on the low-part (one for the
symbol being referenced and one for the high-part reloc). The
indirect approach seems cleaner to me.

An example might clarify:

0x1234: auipc t0, %pcrel_hi(sym)
...
0x1338: addi t0, t0, %prcrel_lo(0x1234)
...
sym = 0x45678

The %pcrel_lo needs to be filled in with ((0x45678 - 0x1234) & 0xFFF).

This approach is perhaps unconventional, but it is hard to see why it
is "seriously wrong."
Post by Alan Modra
--
Alan Modra
Australia Development Lab, IBM
Alan Modra
2016-10-12 23:41:04 UTC
Permalink
Post by Andrew Waterman
Post by Alan Modra
Post by Alan Modra
Post by Andrew Waterman
+/* Remember all PC-relative high-part relocs we've encountered to help
us
Post by Andrew Waterman
+ later resolve the corresponding low-part relocs. */
Why? This sort of thing is usually only needed on REL targets.
We'll expound on this comment to explain our strategy. Of course, a simpler
approach might suffice.
It's not a matter of explaining. I think you have something seriously
wrong here. You most likely need to remove all of the hi/lo recording
and use of high value to apply low relocs, or you have a broken ABI.
If the latter then it would pay to fix it sooner rather than later.
The reason hi/lo matching is needed on REL targets is that with the
addend stored in the insn you can only fit a partial addend in an
insn. You need to read both insns and combine the addends to create a
full addend (which is needed to properly perform pc subtraction).
With RELA targets you should have the full addend in the reloc.
It's not that a partial addend is being stored anywhere; it's that
there is a level of indirection. The PC-relative addressing scheme is
relative to the address of the high-part reloc, because of how the ISA
works. So, the value of the low-part reloc depends both on the
address of the high-part reloc and the symbol being referenced. The
alternative would be to put two relocs on the low-part (one for the
symbol being referenced and one for the high-part reloc). The
indirect approach seems cleaner to me.
0x1234: auipc t0, %pcrel_hi(sym)
...
0x1338: addi t0, t0, %prcrel_lo(0x1234)
...
sym = 0x45678
The %pcrel_lo needs to be filled in with ((0x45678 - 0x1234) & 0xFFF).
This approach is perhaps unconventional, but it is hard to see why it
is "seriously wrong."
I see. Yes, if you explicitly reference the hi reloc from the lo one
that's not so bad. I thought you may have been trying to associate
the two in the linker, which has lots of ways to go wrong.

Note that power9 has something similar with addpcis/addi pairs where
we write:

.L0:
addpcis 9,(sym - .L0)@ha
...
addi 9,9,(sym - .L0)@l

producing (... is two nops in this example)

0000000000000000 <.text>:
0: 04 00 20 4d addpcis r9,0
0: R_PPC64_REL16DX_HA sym
4: 00 00 00 60 nop
8: 00 00 00 60 nop
c: 00 00 29 39 addi r9,r9,0
c: R_PPC64_REL16_LO sym+0xc

This way both addpcis and addi insns have exactly the same reloc
symbol and each can be relocated independently. The addpcis insn
reloc has an addend of -.L0, zero in this case, while the addi insn
reloc addend is the difference between the two insn addresses.

Things get a little tricky with linker relaxation involving deletion
or insertion of insns (which powerpc64 ld doesn't support), but I
imagine you might have similar problems if linker relaxation moves
your auipc insn.
--
Alan Modra
Australia Development Lab, IBM
Andrew Waterman
2016-10-12 23:59:22 UTC
Permalink
Post by Alan Modra
Post by Andrew Waterman
Post by Alan Modra
Post by Alan Modra
Post by Andrew Waterman
+/* Remember all PC-relative high-part relocs we've encountered to help
us
Post by Andrew Waterman
+ later resolve the corresponding low-part relocs. */
Why? This sort of thing is usually only needed on REL targets.
We'll expound on this comment to explain our strategy. Of course, a simpler
approach might suffice.
It's not a matter of explaining. I think you have something seriously
wrong here. You most likely need to remove all of the hi/lo recording
and use of high value to apply low relocs, or you have a broken ABI.
If the latter then it would pay to fix it sooner rather than later.
The reason hi/lo matching is needed on REL targets is that with the
addend stored in the insn you can only fit a partial addend in an
insn. You need to read both insns and combine the addends to create a
full addend (which is needed to properly perform pc subtraction).
With RELA targets you should have the full addend in the reloc.
It's not that a partial addend is being stored anywhere; it's that
there is a level of indirection. The PC-relative addressing scheme is
relative to the address of the high-part reloc, because of how the ISA
works. So, the value of the low-part reloc depends both on the
address of the high-part reloc and the symbol being referenced. The
alternative would be to put two relocs on the low-part (one for the
symbol being referenced and one for the high-part reloc). The
indirect approach seems cleaner to me.
0x1234: auipc t0, %pcrel_hi(sym)
...
0x1338: addi t0, t0, %prcrel_lo(0x1234)
...
sym = 0x45678
The %pcrel_lo needs to be filled in with ((0x45678 - 0x1234) & 0xFFF).
This approach is perhaps unconventional, but it is hard to see why it
is "seriously wrong."
I see. Yes, if you explicitly reference the hi reloc from the lo one
that's not so bad. I thought you may have been trying to associate
the two in the linker, which has lots of ways to go wrong.
I'm glad we concur!
Post by Alan Modra
Note that power9 has something similar with addpcis/addi pairs where
...
producing (... is two nops in this example)
0: 04 00 20 4d addpcis r9,0
0: R_PPC64_REL16DX_HA sym
4: 00 00 00 60 nop
8: 00 00 00 60 nop
c: 00 00 29 39 addi r9,r9,0
c: R_PPC64_REL16_LO sym+0xc
This way both addpcis and addi insns have exactly the same reloc
symbol and each can be relocated independently. The addpcis insn
reloc has an addend of -.L0, zero in this case, while the addi insn
reloc addend is the difference between the two insn addresses.
Things get a little tricky with linker relaxation involving deletion
or insertion of insns (which powerpc64 ld doesn't support), but I
imagine you might have similar problems if linker relaxation moves
your auipc insn.
I didn't realize another port had to address a similar issue. Thanks
for the pointer.

The indirect approach is tolerant to intervening linker relaxations,
because the delta between hi and lo doesn't factor into the final
computation; in the end, it's just the LSBs of (sym - hi). The power9
approach seems cleaner if the delta can be computed at assembly time,
but relaxation does preclude that.
Post by Alan Modra
--
Alan Modra
Australia Development Lab, IBM
Andrew Waterman
2016-10-11 23:46:09 UTC
Permalink
---
include/opcode/riscv-opc.h | 1160 ++++++++++++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 340 +++++++++++++
opcodes/riscv-dis.c | 502 +++++++++++++++++++
opcodes/riscv-opc.c | 616 +++++++++++++++++++++++
4 files changed, 2618 insertions(+)
create mode 100644 include/opcode/riscv-opc.h
create mode 100644 include/opcode/riscv.h
create mode 100644 opcodes/riscv-dis.c
create mode 100644 opcodes/riscv-opc.c

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
new file mode 100644
index 0000000..4369eac
--- /dev/null
+++ b/include/opcode/riscv-opc.h
@@ -0,0 +1,1160 @@
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_SLLI_RV32 0x1013
+#define MASK_SLLI_RV32 0xfe00707f
+#define MATCH_SRLI_RV32 0x5013
+#define MASK_SRLI_RV32 0xfe00707f
+#define MATCH_SRAI_RV32 0x40005013
+#define MASK_SRAI_RV32 0xfe00707f
+#define MATCH_FRFLAGS 0x102073
+#define MASK_FRFLAGS 0xfffff07f
+#define MATCH_FSFLAGS 0x101073
+#define MASK_FSFLAGS 0xfff0707f
+#define MATCH_FSFLAGSI 0x105073
+#define MASK_FSFLAGSI 0xfff0707f
+#define MATCH_FRRM 0x202073
+#define MASK_FRRM 0xfffff07f
+#define MATCH_FSRM 0x201073
+#define MASK_FSRM 0xfff0707f
+#define MATCH_FSRMI 0x205073
+#define MASK_FSRMI 0xfff0707f
+#define MATCH_FSCSR 0x301073
+#define MASK_FSCSR 0xfff0707f
+#define MATCH_FRCSR 0x302073
+#define MASK_FRCSR 0xfffff07f
+#define MATCH_RDCYCLE 0xc0002073
+#define MASK_RDCYCLE 0xfffff07f
+#define MATCH_RDTIME 0xc0102073
+#define MASK_RDTIME 0xfffff07f
+#define MATCH_RDINSTRET 0xc0202073
+#define MASK_RDINSTRET 0xfffff07f
+#define MATCH_RDCYCLEH 0xc8002073
+#define MASK_RDCYCLEH 0xfffff07f
+#define MATCH_RDTIMEH 0xc8102073
+#define MASK_RDTIMEH 0xfffff07f
+#define MATCH_RDINSTRETH 0xc8202073
+#define MASK_RDINSTRETH 0xfffff07f
+#define MATCH_SCALL 0x73
+#define MASK_SCALL 0xffffffff
+#define MATCH_SBREAK 0x100073
+#define MASK_SBREAK 0xffffffff
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM 0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
new file mode 100644
index 0000000..4679b9a
--- /dev/null
+++ b/include/opcode/riscv.h
@@ -0,0 +1,340 @@
+/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
+ Copyright 2011
+ Free Software Foundation, Inc.
+ Contributed by Andrew Waterman
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING. If not, write to the Free
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#ifndef _RISCV_H_
+#define _RISCV_H_
+
+#include "riscv-opc.h"
+#include <stdlib.h>
+#include <stdint.h>
+
+typedef uint64_t insn_t;
+
+static inline unsigned int riscv_insn_length (insn_t insn)
+{
+ if ((insn & 0x3) != 0x3) /* RVC. */
+ return 2;
+ if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */
+ return 4;
+ if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */
+ return 6;
+ if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */
+ return 8;
+ /* Longer instructions not supported at the moment. */
+ return 2;
+}
+
+static const char * const riscv_rm[8] = {
+ "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
+};
+static const char * const riscv_pred_succ[16] = {
+ 0, "w", "r", "rw", "o", "ow", "or", "orw",
+ "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
+};
+
+#define RVC_JUMP_BITS 11
+#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
+
+#define RVC_BRANCH_BITS 8
+#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
+
+#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
+
+#define EXTRACT_ITYPE_IMM(x) \
+ (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
+#define EXTRACT_STYPE_IMM(x) \
+ (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
+#define EXTRACT_SBTYPE_IMM(x) \
+ ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
+#define EXTRACT_UTYPE_IMM(x) \
+ ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
+#define EXTRACT_UJTYPE_IMM(x) \
+ ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
+#define EXTRACT_RVC_IMM(x) \
+ (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
+#define EXTRACT_RVC_LUI_IMM(x) \
+ (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
+#define EXTRACT_RVC_SIMM3(x) \
+ (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
+#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
+ ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
+#define EXTRACT_RVC_ADDI16SP_IMM(x) \
+ ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
+#define EXTRACT_RVC_LW_IMM(x) \
+ ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
+#define EXTRACT_RVC_LD_IMM(x) \
+ ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
+#define EXTRACT_RVC_LWSP_IMM(x) \
+ ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
+#define EXTRACT_RVC_LDSP_IMM(x) \
+ ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
+#define EXTRACT_RVC_SWSP_IMM(x) \
+ ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
+#define EXTRACT_RVC_SDSP_IMM(x) \
+ ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
+#define EXTRACT_RVC_B_IMM(x) \
+ ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
+#define EXTRACT_RVC_J_IMM(x) \
+ ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
+
+#define ENCODE_ITYPE_IMM(x) \
+ (RV_X(x, 0, 12) << 20)
+#define ENCODE_STYPE_IMM(x) \
+ ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
+#define ENCODE_SBTYPE_IMM(x) \
+ ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
+#define ENCODE_UTYPE_IMM(x) \
+ (RV_X(x, 12, 20) << 12)
+#define ENCODE_UJTYPE_IMM(x) \
+ ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
+#define ENCODE_RVC_IMM(x) \
+ ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
+#define ENCODE_RVC_LUI_IMM(x) \
+ ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
+#define ENCODE_RVC_SIMM3(x) \
+ (RV_X(x, 0, 3) << 10)
+#define ENCODE_RVC_ADDI4SPN_IMM(x) \
+ ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
+#define ENCODE_RVC_ADDI16SP_IMM(x) \
+ ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
+#define ENCODE_RVC_LW_IMM(x) \
+ ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
+#define ENCODE_RVC_LD_IMM(x) \
+ ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
+#define ENCODE_RVC_LWSP_IMM(x) \
+ ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
+#define ENCODE_RVC_LDSP_IMM(x) \
+ ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
+#define ENCODE_RVC_SWSP_IMM(x) \
+ ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
+#define ENCODE_RVC_SDSP_IMM(x) \
+ ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
+#define ENCODE_RVC_B_IMM(x) \
+ ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
+#define ENCODE_RVC_J_IMM(x) \
+ ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
+
+#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
+#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
+#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
+#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
+#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
+#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
+#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
+#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
+#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
+#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
+#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
+#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
+#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
+#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
+#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
+#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
+#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
+#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
+
+#define RISCV_RTYPE(insn, rd, rs1, rs2) \
+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
+#define RISCV_ITYPE(insn, rd, rs1, imm) \
+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
+#define RISCV_STYPE(insn, rs1, rs2, imm) \
+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
+#define RISCV_SBTYPE(insn, rs1, rs2, target) \
+ ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
+#define RISCV_UTYPE(insn, rd, bigimm) \
+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
+#define RISCV_UJTYPE(insn, rd, target) \
+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
+
+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
+#define RVC_NOP MATCH_C_ADDI
+
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
+#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
+#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
+
+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
+#define RISCV_JUMP_ALIGN_BITS 1
+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
+#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
+
+#define RISCV_IMM_BITS 12
+#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
+#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
+#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
+#define RISCV_RVC_IMM_REACH (1LL << 6)
+#define RISCV_BRANCH_BITS RISCV_IMM_BITS
+#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
+#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
+#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
+
+/* RV fields. */
+
+#define OP_MASK_OP 0x7f
+#define OP_SH_OP 0
+#define OP_MASK_RS2 0x1f
+#define OP_SH_RS2 20
+#define OP_MASK_RS1 0x1f
+#define OP_SH_RS1 15
+#define OP_MASK_RS3 0x1f
+#define OP_SH_RS3 27
+#define OP_MASK_RD 0x1f
+#define OP_SH_RD 7
+#define OP_MASK_SHAMT 0x3f
+#define OP_SH_SHAMT 20
+#define OP_MASK_SHAMTW 0x1f
+#define OP_SH_SHAMTW 20
+#define OP_MASK_RM 0x7
+#define OP_SH_RM 12
+#define OP_MASK_PRED 0xf
+#define OP_SH_PRED 24
+#define OP_MASK_SUCC 0xf
+#define OP_SH_SUCC 20
+#define OP_MASK_AQ 0x1
+#define OP_SH_AQ 26
+#define OP_MASK_RL 0x1
+#define OP_SH_RL 25
+
+#define OP_MASK_CUSTOM_IMM 0x7f
+#define OP_SH_CUSTOM_IMM 25
+#define OP_MASK_CSR 0xfff
+#define OP_SH_CSR 20
+
+/* RVC fields. */
+
+#define OP_MASK_CRS2 0x1f
+#define OP_SH_CRS2 2
+#define OP_MASK_CRS1S 0x7
+#define OP_SH_CRS1S 7
+#define OP_MASK_CRS2S 0x7
+#define OP_SH_CRS2S 2
+
+/* ABI names for selected x-registers. */
+
+#define X_RA 1
+#define X_SP 2
+#define X_GP 3
+#define X_TP 4
+#define X_T0 5
+#define X_T1 6
+#define X_T2 7
+#define X_T3 28
+
+#define NGPR 32
+#define NFPR 32
+
+/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
+ VALUE << SHIFT. VALUE is evaluated exactly once. */
+#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
+ (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
+ | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
+
+/* Extract bits MASK << SHIFT from STRUCT and shift them right
+ SHIFT places. */
+#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
+ (((STRUCT) >> (SHIFT)) & (MASK))
+
+/* Extract the operand given by FIELD from integer INSN. */
+#define EXTRACT_OPERAND(FIELD, INSN) \
+ EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
+
+/* This structure holds information for a particular instruction. */
+
+struct riscv_opcode
+{
+ /* The name of the instruction. */
+ const char *name;
+ /* The ISA subset name (I, M, A, F, D, Xextension). */
+ const char *subset;
+ /* A string describing the arguments for this instruction. */
+ const char *args;
+ /* The basic opcode for the instruction. When assembling, this
+ opcode is modified by the arguments to produce the actual opcode
+ that is used. If pinfo is INSN_MACRO, then this is 0. */
+ insn_t match;
+ /* If pinfo is not INSN_MACRO, then this is a bit mask for the
+ relevant portions of the opcode when disassembling. If the
+ actual opcode anded with the match field equals the opcode field,
+ then we have found the correct instruction. If pinfo is
+ INSN_MACRO, then this field is the macro identifier. */
+ insn_t mask;
+ /* A function to determine if a word corresponds to this instruction.
+ Usually, this computes ((word & mask) == match). */
+ int (*match_func) (const struct riscv_opcode *op, insn_t word);
+ /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
+ of bits describing the instruction, notably any relevant hazard
+ information. */
+ unsigned long pinfo;
+};
+
+/* Instruction is a simple alias (e.g. "mv" for "addi"). */
+#define INSN_ALIAS 0x00000001
+/* Instruction is actually a macro. It should be ignored by the
+ disassembler, and requires special treatment by the assembler. */
+#define INSN_MACRO 0xffffffff
+
+/* This is a list of macro expanded instructions.
+
+ _I appended means immediate
+ _A appended means address
+ _AB appended means address with base register
+ _D appended means 64 bit floating point constant
+ _S appended means 32 bit floating point constant. */
+
+enum
+{
+ M_LA,
+ M_LLA,
+ M_LA_TLS_GD,
+ M_LA_TLS_IE,
+ M_LB,
+ M_LBU,
+ M_LH,
+ M_LHU,
+ M_LW,
+ M_LWU,
+ M_LD,
+ M_SB,
+ M_SH,
+ M_SW,
+ M_SD,
+ M_FLW,
+ M_FLD,
+ M_FSW,
+ M_FSD,
+ M_CALL,
+ M_J,
+ M_LI,
+ M_NUM_MACROS
+};
+
+
+extern const char * const riscv_gpr_names_numeric[NGPR];
+extern const char * const riscv_gpr_names_abi[NGPR];
+extern const char * const riscv_fpr_names_numeric[NFPR];
+extern const char * const riscv_fpr_names_abi[NFPR];
+
+extern const struct riscv_opcode riscv_opcodes[];
+
+#endif /* _RISCV_H_ */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
new file mode 100644
index 0000000..fe5e5a8
--- /dev/null
+++ b/opcodes/riscv-dis.c
@@ -0,0 +1,502 @@
+/* RISC-V disassembler
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on MIPS target.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "dis-asm.h"
+#include "libiberty.h"
+#include "opcode/riscv.h"
+#include "opintl.h"
+#include "elf-bfd.h"
+#include "elf/riscv.h"
+
+#include <stdint.h>
+#include <ctype.h>
+
+struct riscv_private_data
+{
+ bfd_vma gp;
+ bfd_vma print_addr;
+ bfd_vma hi_addr[OP_MASK_RD + 1];
+};
+
+static const char * const *riscv_gpr_names;
+static const char * const *riscv_fpr_names;
+
+/* Other options */
+static int no_aliases; /* If set disassemble as most general inst. */
+
+static void
+set_default_riscv_dis_options (void)
+{
+ riscv_gpr_names = riscv_gpr_names_abi;
+ riscv_fpr_names = riscv_fpr_names_abi;
+ no_aliases = 0;
+}
+
+static void
+parse_riscv_dis_option (const char *option)
+{
+ if (strcmp (option, "no-aliases") == 0)
+ no_aliases = 1;
+ else if (strcmp (option, "numeric") == 0)
+ {
+ riscv_gpr_names = riscv_gpr_names_numeric;
+ riscv_fpr_names = riscv_fpr_names_numeric;
+ }
+ else
+ {
+ /* Invalid option. */
+ fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
+ }
+}
+
+static void
+parse_riscv_dis_options (const char *opts_in)
+{
+ char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
+
+ set_default_riscv_dis_options ();
+
+ for ( ; opt_end != NULL; opt = opt_end + 1)
+ {
+ if ((opt_end = strchr (opt, ',')) != NULL)
+ *opt_end = 0;
+ parse_riscv_dis_option (opt);
+ }
+
+ free (opts);
+}
+
+/* Print one argument from an array. */
+
+static void
+arg_print (struct disassemble_info *info, unsigned long val,
+ const char* const* array, size_t size)
+{
+ const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
+ (*info->fprintf_func) (info->stream, "%s", s);
+}
+
+static void
+maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
+{
+ if (pd->hi_addr[base_reg] != (bfd_vma)-1)
+ {
+ pd->print_addr = pd->hi_addr[base_reg] + offset;
+ pd->hi_addr[base_reg] = -1;
+ }
+ else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
+ pd->print_addr = pd->gp + offset;
+ else if (base_reg == X_TP || base_reg == 0)
+ pd->print_addr = offset;
+}
+
+/* Print insn arguments for 32/64-bit code. */
+
+static void
+print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+{
+ struct riscv_private_data *pd = info->private_data;
+ int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
+ int rd = (l >> OP_SH_RD) & OP_MASK_RD;
+ fprintf_ftype print = info->fprintf_func;
+
+ if (*d != '\0')
+ print (info->stream, "\t");
+
+ for (; *d != '\0'; d++)
+ {
+ switch (*d)
+ {
+ case 'C': /* RVC */
+ switch (*++d)
+ {
+ case 's': /* RS1 x8-x15 */
+ case 'w': /* RS1 x8-x15 */
+ print (info->stream, "%s",
+ riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
+ break;
+ case 't': /* RS2 x8-x15 */
+ case 'x': /* RS2 x8-x15 */
+ print (info->stream, "%s",
+ riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
+ break;
+ case 'U': /* RS1, constrained to equal RD */
+ print (info->stream, "%s", riscv_gpr_names[rd]);
+ break;
+ case 'c': /* RS1, constrained to equal sp */
+ print (info->stream, "%s", riscv_gpr_names[X_SP]);
+ break;
+ case 'V': /* RS2 */
+ print (info->stream, "%s",
+ riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
+ break;
+ case 'i':
+ print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
+ break;
+ case 'j':
+ print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
+ break;
+ case 'k':
+ print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
+ break;
+ case 'l':
+ print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
+ break;
+ case 'm':
+ print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
+ break;
+ case 'n':
+ print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
+ break;
+ case 'K':
+ print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
+ break;
+ case 'L':
+ print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
+ break;
+ case 'M':
+ print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
+ break;
+ case 'N':
+ print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
+ break;
+ case 'p':
+ info->target = EXTRACT_RVC_B_IMM (l) + pc;
+ (*info->print_address_func) (info->target, info);
+ break;
+ case 'a':
+ info->target = EXTRACT_RVC_J_IMM (l) + pc;
+ (*info->print_address_func) (info->target, info);
+ break;
+ case 'u':
+ print (info->stream, "0x%x",
+ (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
+ break;
+ case '>':
+ print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
+ break;
+ case '<':
+ print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
+ break;
+ case 'T': /* floating-point RS2 */
+ print (info->stream, "%s",
+ riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
+ break;
+ case 'D': /* floating-point RS2 x8-x15 */
+ print (info->stream, "%s",
+ riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
+ break;
+ }
+ break;
+
+ case ',':
+ case '(':
+ case ')':
+ case '[':
+ case ']':
+ print (info->stream, "%c", *d);
+ break;
+
+ case '0':
+ /* Only print constant 0 if it is the last argument */
+ if (!d[1])
+ print (info->stream, "0");
+ break;
+
+ case 'b':
+ case 's':
+ print (info->stream, "%s", riscv_gpr_names[rs1]);
+ break;
+
+ case 't':
+ print (info->stream, "%s",
+ riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
+ break;
+
+ case 'u':
+ print (info->stream, "0x%x",
+ (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
+ break;
+
+ case 'm':
+ arg_print (info, EXTRACT_OPERAND (RM, l),
+ riscv_rm, ARRAY_SIZE (riscv_rm));
+ break;
+
+ case 'P':
+ arg_print (info, EXTRACT_OPERAND (PRED, l),
+ riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
+ break;
+
+ case 'Q':
+ arg_print (info, EXTRACT_OPERAND (SUCC, l),
+ riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
+ break;
+
+ case 'o':
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
+ case 'j':
+ if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
+ || (l & MASK_JALR) == MATCH_JALR)
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
+ break;
+
+ case 'q':
+ maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
+ print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
+ break;
+
+ case 'a':
+ info->target = EXTRACT_UJTYPE_IMM (l) + pc;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'p':
+ info->target = EXTRACT_SBTYPE_IMM (l) + pc;
+ (*info->print_address_func) (info->target, info);
+ break;
+
+ case 'd':
+ if ((l & MASK_AUIPC) == MATCH_AUIPC)
+ pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
+ else if ((l & MASK_LUI) == MATCH_LUI)
+ pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
+ else if ((l & MASK_C_LUI) == MATCH_C_LUI)
+ pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
+ print (info->stream, "%s", riscv_gpr_names[rd]);
+ break;
+
+ case 'z':
+ print (info->stream, "%s", riscv_gpr_names[0]);
+ break;
+
+ case '>':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
+ break;
+
+ case '<':
+ print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
+ break;
+
+ case 'S':
+ case 'U':
+ print (info->stream, "%s", riscv_fpr_names[rs1]);
+ break;
+
+ case 'T':
+ print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
+ break;
+
+ case 'D':
+ print (info->stream, "%s", riscv_fpr_names[rd]);
+ break;
+
+ case 'R':
+ print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
+ break;
+
+ case 'E':
+ {
+ const char* csr_name = NULL;
+ unsigned int csr = EXTRACT_OPERAND (CSR, l);
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ if (csr_name)
+ print (info->stream, "%s", csr_name);
+ else
+ print (info->stream, "0x%x", csr);
+ break;
+ }
+
+ case 'Z':
+ print (info->stream, "%d", rs1);
+ break;
+
+ default:
+ /* xgettext:c-format */
+ print (info->stream, _("# internal error, undefined modifier (%c)"),
+ *d);
+ return;
+ }
+ }
+}
+
+/* Print the RISC-V instruction at address MEMADDR in debugged memory,
+ on using INFO. Returns length of the instruction, in bytes.
+ BIGENDIAN must be 1 if this is big-endian code, 0 if
+ this is little-endian code. */
+
+static int
+riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
+{
+ const struct riscv_opcode *op;
+ static bfd_boolean init = 0;
+ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
+ struct riscv_private_data *pd;
+ int insnlen;
+
+#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
+
+ /* Build a hash table to shorten the search time. */
+ if (! init)
+ {
+ for (op = riscv_opcodes; op->name; op++)
+ if (!riscv_hash[OP_HASH_IDX (op->match)])
+ riscv_hash[OP_HASH_IDX (op->match)] = op;
+
+ init = 1;
+ }
+
+ if (info->private_data == NULL)
+ {
+ int i;
+
+ pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
+ pd->gp = -1;
+ pd->print_addr = -1;
+ for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
+ pd->hi_addr[i] = -1;
+
+ for (i = 0; i < info->symtab_size; i++)
+ if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0)
+ pd->gp = bfd_asymbol_value (info->symtab[i]);
+ }
+ else
+ pd = info->private_data;
+
+ insnlen = riscv_insn_length (word);
+
+ info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
+ info->bytes_per_line = 8;
+ info->display_endian = info->endian;
+ info->insn_info_valid = 1;
+ info->branch_delay_insns = 0;
+ info->data_size = 0;
+ info->insn_type = dis_nonbranch;
+ info->target = 0;
+ info->target2 = 0;
+
+ op = riscv_hash[OP_HASH_IDX (word)];
+ if (op != NULL)
+ {
+ int xlen = 0;
+
+ /* The incoming section might not always be complete. */
+ if (info->section != NULL)
+ {
+ Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
+ xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
+ }
+
+ for (; op->name; op++)
+ {
+ /* Does the opcode match? */
+ if (! (op->match_func) (op, word))
+ continue;
+ /* Is this a pseudo-instruction and may we print it as such? */
+ if (no_aliases && (op->pinfo & INSN_ALIAS))
+ continue;
+ /* Is this instruction restricted to a certain value of XLEN? */
+ if (isdigit (op->subset[0]) && atoi (op->subset) != xlen)
+ continue;
+
+ /* It's a match. */
+ (*info->fprintf_func) (info->stream, "%s", op->name);
+ print_insn_args (op->args, word, memaddr, info);
+
+ /* Try to disassemble multi-instruction addressing sequences. */
+ if (pd->print_addr != (bfd_vma)-1)
+ {
+ info->target = pd->print_addr;
+ (*info->fprintf_func) (info->stream, " # ");
+ (*info->print_address_func) (info->target, info);
+ pd->print_addr = -1;
+ }
+
+ return insnlen;
+ }
+ }
+
+ /* We did not find a match, so just print the instruction bits. */
+ info->insn_type = dis_noninsn;
+ (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
+ return insnlen;
+}
+
+int
+print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
+{
+ bfd_byte packet[2];
+ insn_t insn = 0;
+ bfd_vma n;
+ int status;
+
+ if (info->disassembler_options != NULL)
+ {
+ parse_riscv_dis_options (info->disassembler_options);
+ /* Avoid repeatedly parsing the options. */
+ info->disassembler_options = NULL;
+ }
+ else if (riscv_gpr_names == NULL)
+ set_default_riscv_dis_options ();
+
+ /* Instructions are a sequence of 2-byte packets in little-endian order. */
+ for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
+ {
+ status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
+ if (status != 0)
+ {
+ /* Don't fail just because we fell off the end. */
+ if (n > 0)
+ break;
+ (*info->memory_error_func) (status, memaddr, info);
+ return status;
+ }
+
+ insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
+ }
+
+ return riscv_disassemble_insn (memaddr, insn, info);
+}
+
+void
+print_riscv_disassembler_options (FILE *stream)
+{
+ fprintf (stream, _("\n\
+The following RISC-V-specific disassembler options are supported for use\n\
+with the -M switch (multiple options should be separated by commas):\n"));
+
+ fprintf (stream, _("\n\
+ numeric Print numeric reigster names, rather than ABI names.\n"));
+
+ fprintf (stream, _("\n\
+ no-aliases Disassemble only into canonical instructions, rather\n\
+ than into pseudoinstructions.\n"));
+
+ fprintf (stream, _("\n"));
+}
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
new file mode 100644
index 0000000..b963f58
--- /dev/null
+++ b/opcodes/riscv-opc.c
@@ -0,0 +1,616 @@
+/* RISC-V opcode list
+ Copyright 2011-2015 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (***@sifive.com).
+ Based on MIPS target.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+#include "sysdep.h"
+#include "opcode/riscv.h"
+#include <stdio.h>
+
+/* Register names used by gas and objdump. */
+
+const char * const riscv_gpr_names_numeric[NGPR] =
+{
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
+};
+
+const char * const riscv_gpr_names_abi[NGPR] = {
+ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
+ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
+ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
+};
+
+const char * const riscv_fpr_names_numeric[NFPR] =
+{
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
+};
+
+const char * const riscv_fpr_names_abi[NFPR] = {
+ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
+ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
+ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+};
+
+/* The order of overloaded instructions matters. Label arguments and
+ register arguments look the same. Instructions that can have either
+ for arguments must apear in the correct order in this table for the
+ assembler to pick the right one. In other words, entries with
+ immediate operands must apear after the same instruction with
+ registers.
+
+ Because of the lookup algorithm used, entries with the same opcode
+ name must be contiguous. */
+
+#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
+#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
+#define MASK_RD (OP_MASK_RD << OP_SH_RD)
+#define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
+#define MASK_IMM ENCODE_ITYPE_IMM(-1U)
+#define MASK_RVC_IMM ENCODE_RVC_IMM(-1U)
+#define MASK_UIMM ENCODE_UTYPE_IMM(-1U)
+#define MASK_RM (OP_MASK_RM << OP_SH_RM)
+#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED)
+#define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC)
+#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
+#define MASK_RL (OP_MASK_RL << OP_SH_RL)
+#define MASK_AQRL (MASK_AQ | MASK_RL)
+
+static int match_opcode(const struct riscv_opcode *op, insn_t insn)
+{
+ return ((insn ^ op->match) & op->mask) == 0;
+}
+
+static int match_never(const struct riscv_opcode *op ATTRIBUTE_UNUSED,
+ insn_t insn ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+static int match_rs1_eq_rs2(const struct riscv_opcode *op, insn_t insn)
+{
+ int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
+ int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
+ return match_opcode (op, insn) && rs1 == rs2;
+}
+
+static int match_rd_nonzero(const struct riscv_opcode *op, insn_t insn)
+{
+ return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
+}
+
+static int match_c_add(const struct riscv_opcode *op, insn_t insn)
+{
+ return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
+}
+
+static int match_c_lui(const struct riscv_opcode *op, insn_t insn)
+{
+ return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2);
+}
+
+const struct riscv_opcode riscv_opcodes[] =
+{
+/* name, isa, operands, match, mask, match_func, pinfo */
+{"unimp", "C", "", 0, 0xffffU, match_opcode, 0 },
+{"unimp", "I", "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
+{"ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
+{"ebreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
+{"sbreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
+{"sbreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS },
+{"ret", "C", "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS },
+{"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
+{"jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS },
+{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS },
+{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS },
+{"jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS },
+{"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS },
+{"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS },
+{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS },
+{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, 0 },
+{"j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS },
+{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
+{"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
+{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
+{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, 0 },
+{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
+{"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
+{"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
+{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO },
+{"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
+{"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
+{"lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
+{"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 },
+{"li", "C", "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
+{"li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
+{"li", "C", "d,0", MATCH_C_LI, MASK_C_LI | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
+{"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */
+{"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO },
+{"mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
+{"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
+{"move", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
+{"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
+{"andi", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
+{"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
+{"and", "C", "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
+{"and", "C", "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
+{"and", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
+{"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 },
+{"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
+{"beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS },
+{"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS },
+{"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, 0 },
+{"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS },
+{"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS },
+{"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS },
+{"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS },
+{"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, 0 },
+{"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, 0 },
+{"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS },
+{"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS },
+{"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, 0 },
+{"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, 0 },
+{"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS },
+{"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS },
+{"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS },
+{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS },
+{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 },
+{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
+{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
+{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
+{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
+{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
+{"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
+{"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
+{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
+{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
+{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
+{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
+{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
+{"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO },
+{"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO },
+{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO },
+{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO },
+{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
+{"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
+{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
+{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
+{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 },
+{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
+{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
+{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
+{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
+{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 },
+{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
+{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
+{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
+{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
+{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 },
+{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
+{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
+{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 },
+{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, 0 },
+{"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO },
+{"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, 0 },
+{"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO },
+{"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, 0 },
+{"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO },
+{"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, 0 },
+{"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO },
+{"lw", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS },
+{"lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS },
+{"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, 0 },
+{"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
+{"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS },
+{"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
+{"or", "C", "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
+{"or", "C", "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
+{"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 },
+{"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
+{"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
+{"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
+{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
+{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
+{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
+{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
+{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
+{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
+{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
+{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
+{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },
+{"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS },
+{"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS },
+{"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, 0 },
+{"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO },
+{"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, 0 },
+{"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO },
+{"sw", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS },
+{"sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS },
+{"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, 0 },
+{"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
+{"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
+{"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
+{"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
+{"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, 0 },
+{"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, 0 },
+{"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, 0 },
+{"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, 0 },
+{"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, 0 },
+{"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, 0 },
+{"ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
+{"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
+{"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 },
+{"xor", "C", "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
+{"xor", "C", "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
+{"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 },
+{"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
+{"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, 0 },
+{"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO },
+{"ld", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS },
+{"ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS },
+{"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 },
+{"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO },
+{"sd", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS },
+{"sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS },
+{"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, 0 },
+{"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
+{"sext.w", "64C", "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
+{"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS },
+{"addiw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
+{"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
+{"addw", "64C", "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
+{"addw", "64C", "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
+{"addw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
+{"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 },
+{"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS },
+{"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
+{"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
+{"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 },
+{"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS },
+{"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
+{"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 },
+{"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS },
+{"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
+{"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 },
+{"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS },
+{"subw", "64C", "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS },
+{"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
+
+/* Atomic memory operation instruction subset */
+{"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
+{"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
+{"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
+{"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
+{"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
+{"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
+{"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
+{"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
+{"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
+{"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
+{"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
+{"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
+{"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
+{"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
+{"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
+{"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
+{"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
+{"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
+{"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
+{"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
+{"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
+{"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
+{"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
+{"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
+{"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
+{"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
+{"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
+{"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
+{"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
+{"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
+{"lr.w.sc", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
+{"sc.w.sc", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
+{"amoadd.w.sc", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
+{"amoswap.w.sc", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
+{"amoand.w.sc", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
+{"amoor.w.sc", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
+{"amoxor.w.sc", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
+{"amomax.w.sc", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.w.sc", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
+{"amomin.w.sc", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
+{"amominu.w.sc", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
+{"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
+{"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
+{"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
+{"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
+{"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
+{"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
+{"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
+{"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
+{"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
+{"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
+{"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
+{"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
+{"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
+{"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
+{"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
+{"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
+{"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
+{"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
+{"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
+{"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
+{"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
+{"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
+{"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
+{"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
+{"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
+{"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
+{"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
+{"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
+{"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
+{"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
+{"lr.d.sc", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
+{"sc.d.sc", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
+{"amoadd.d.sc", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
+{"amoswap.d.sc", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
+{"amoand.d.sc", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
+{"amoor.d.sc", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
+{"amoxor.d.sc", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
+{"amomax.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
+{"amomaxu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
+{"amomin.d.sc", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
+{"amominu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
+
+/* Multiply/Divide instruction subset */
+{"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
+{"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
+{"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
+{"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
+{"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 },
+{"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
+{"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 },
+{"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 },
+{"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
+{"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
+{"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
+{"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
+{"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+
+/* Single-precision floating-point instruction subset */
+{"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
+{"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
+{"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
+{"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
+{"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
+{"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
+{"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
+{"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
+{"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
+{"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
+{"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
+{"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
+{"flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS },
+{"flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS },
+{"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 },
+{"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO },
+{"fsw", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS },
+{"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS },
+{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 },
+{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
+{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
+{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
+{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
+{"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
+{"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
+{"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 },
+{"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
+{"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 },
+{"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
+{"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 },
+{"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
+{"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 },
+{"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
+{"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 },
+{"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
+{"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
+{"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
+{"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 },
+{"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
+{"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 },
+{"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
+{"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 },
+{"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
+{"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 },
+{"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
+{"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 },
+{"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
+{"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 },
+{"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
+{"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 },
+{"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
+{"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 },
+{"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
+{"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
+{"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
+{"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 },
+{"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
+{"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 },
+{"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
+{"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
+{"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
+{"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
+{"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
+
+/* Double-precision floating-point instruction subset */
+{"fld", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS },
+{"fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS },
+{"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, 0 },
+{"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO },
+{"fsd", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS },
+{"fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS },
+{"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, 0 },
+{"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
+{"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
+{"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
+{"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
+{"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 },
+{"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
+{"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 },
+{"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
+{"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 },
+{"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
+{"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 },
+{"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
+{"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 },
+{"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
+{"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
+{"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
+{"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 },
+{"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
+{"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 },
+{"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
+{"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 },
+{"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
+{"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 },
+{"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
+{"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 },
+{"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
+{"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 },
+{"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
+{"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 },
+{"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 },
+{"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 },
+{"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 },
+{"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
+{"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
+{"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
+{"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
+{"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
+{"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
+{"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
+{"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
+{"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
+{"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 },
+{"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
+{"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 },
+{"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
+{"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
+{"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
+{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
+{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
+
+/* Compressed instructions */
+{"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
+{"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 },
+{"c.jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 },
+{"c.j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, 0 },
+{"c.jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 },
+{"c.beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 },
+{"c.bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 },
+{"c.lwsp", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 },
+{"c.lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, 0 },
+{"c.swsp", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 },
+{"c.sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, 0 },
+{"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 },
+{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 },
+{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 },
+{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
+{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
+{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
+{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
+{"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 },
+{"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
+{"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
+{"c.or", "C", "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 },
+{"c.xor", "C", "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
+{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 },
+{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 },
+{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 },
+{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
+{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
+{"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },
+{"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 },
+{"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 },
+{"c.ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, 0 },
+{"c.sdsp", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 },
+{"c.sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, 0 },
+{"c.fldsp", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 },
+{"c.fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 },
+{"c.fsdsp", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 },
+{"c.fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 },
+{"c.flwsp", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 },
+{"c.flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 },
+{"c.fswsp", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 },
+{"c.fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 },
+
+/* Supervisor instructions */
+{"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, 0 },
+{"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 },
+{"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, 0 },
+{"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 },
+{"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 },
+{"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, 0 },
+{"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 },
+{"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 },
+{"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, 0 },
+{"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 },
+{"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
+{"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
+{"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
+{"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
+{"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
+{"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
+{"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
+{"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
+{"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
+{"uret", "I", "", MATCH_URET, MASK_URET, match_opcode, 0 },
+{"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 },
+{"hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 },
+{"mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 },
+{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 },
+{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
+{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
+{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+
+/* Terminate the list. */
+{0, 0, 0, 0, 0, 0, 0}
+};
--
2.7.3
Nick Clifton
2016-10-14 14:39:57 UTC
Permalink
Hi Andrew,
Post by Andrew Waterman
+++ b/include/opcode/riscv-opc.h
@@ -0,0 +1,1160 @@
+/* Automatically generated by parse-opcodes */
If this file is generated by a tool, then that tool (and input files it
requires) should be part of the submission too. Either that, or else
these generated files should be changed to be considered to be the
originals, and no generator mentioned or needed.

The actual patch itself looks reasonably to me, although I have not
yet tested it in a real build. (I am waiting until all of the patches
have been reviewed and, if necessary, updated).

Cheers
Nick
Palmer Dabbelt
2016-10-12 00:13:26 UTC
Permalink
Post by Andrew Waterman
We'd like to submit for inclusion in Binutils a port for the RISC-V
architecture. The port suffices to build a substantial body of software
(including Linux and some 2,000 Fedora packages); so, while it is doubtlessly
not complete, we think it is far enough along to start the upstreaming process.
This port targets Version 2.0 of the RV32I and RV64I base user ISAs, and the
five standard extensions M, A, F, D, and C, all of which are frozen and will
not change over time. It also targets Version 1.9.1 of the RISC-V Privileged
Architectures, which we expect to change somewhat before being standardized
some time in 2017.
The RISC-V community and the 50-some member companies of the RISC-V Foundation
are quite eager to have a single, standard Binutils port. We thank you in
advance for your help in this process and for your feedback on the software
contribution itself.
These patches build on top of 8f1a8fc4df2244f548d55fbecce20b7cd6f90e16, the
latest commit in binutils-gdb.
Sorry, it looks like this got a bit screwed up. Patch 6, which contains the
sim port, was actually too big to make it through the mailing lists. I've
split it up into multiple chunks, but the generated configure script is still
over the limit. The patches are on our github

https://github.com/riscv/riscv-binutils-gdb/commit/8a9083394997bb4a3753844588416ff35ab44dc2
https://github.com/riscv/riscv-binutils-gdb/commit/d1542667f91dcad8e8952362925950d0a81391c6
https://github.com/riscv/riscv-binutils-gdb/commit/5e2c383e5cfa29683ff244d264e9b138203d3c2d

I can re-submit them however is easiest for you guys.

Sorry!
Alan Modra
2016-10-12 01:03:55 UTC
Permalink
Post by Palmer Dabbelt
Sorry, it looks like this got a bit screwed up. Patch 6, which contains the
sim port, was actually too big to make it through the mailing lists. I've
split it up into multiple chunks, but the generated configure script is still
over the limit. The patches are on our github
You can leave out diffs for generated files. Just mention them in
the ChangeLog.
--
Alan Modra
Australia Development Lab, IBM
Nick Clifton
2016-10-14 13:40:13 UTC
Permalink
Hi Andrew,
Post by Andrew Waterman
We'd like to submit for inclusion in Binutils a port for the RISC-V
architecture.
Thanks very much for submitting these patches. Before going any further
though, I have to ask: do all of the authors of these patches have FSF
binutils copyright assignments in place ? I see that SiFive have an
assignment, but are there any other authors involved in this work, and if
so, do they have copyright assignments ?

The next question is: is someone volunteering to be a maintainer for this
port ? A port without a maintainer is likely to bit-rot and eventually be
rendered obsolete. On the other hand volunteering to be a maintainer
should not be taken lightly as it does involve a commitment.

Lastly - are there publicly available documents describing the RISC-V ISA ?
It is handy to be able to refer to these if any questions arise about the
accuracy of the port.

I hope that these questions - and the patch reviews to follow - do not
put you off, and thanks once again for contributing to the binutils.

Cheers
Nick Clifton
Nick Clifton
2016-10-14 14:50:07 UTC
Permalink
Hi Andrew,
Post by Andrew Waterman
We'd like to submit for inclusion in Binutils a port for the RISC-V
architecture.
One other thing that I forgot to mention. It would be helpful if you
could add a patch to binutils/readelf.c to add code for this target.
Specifically I am thinking of updates to these functions:

guess_is_rela
get_machine_name
is_32bit_abs_reloc
is_32bit_pcrel_reloc
is_none_reloc

Hmm, also I see that you are using an EM_RISCV ELF machine number, but
there does not appear to be a patch to include/elf/common.h to add this
value. Did I miss something ?

Cheers
Nick
Joseph Myers
2016-10-14 16:17:35 UTC
Permalink
Post by Nick Clifton
Hmm, also I see that you are using an EM_RISCV ELF machine number, but
there does not appear to be a patch to include/elf/common.h to add this
value. Did I miss something ?
It should be 243 (the last value allocated in
http://www.sco.com/developers/gabi/latest/ch4.eheader.html - if there have
been any e_machine allocations since 23 July 2015, the public ABI has not
been updated with them).
--
Joseph S. Myers
***@codesourcery.com
Nick Clifton
2016-10-17 10:48:27 UTC
Permalink
Hi Joseph,
Post by Joseph Myers
Post by Nick Clifton
Hmm, also I see that you are using an EM_RISCV ELF machine number, but
there does not appear to be a patch to include/elf/common.h to add this
value. Did I miss something ?
It should be 243 (the last value allocated in
http://www.sco.com/developers/gabi/latest/ch4.eheader.html
Ah - we were missing the recent updates to this specification. I have now
checked in a patch to fix this, including adding EM_RISCV.

Cheers
Nick
Palmer Dabbelt
2016-10-15 19:30:28 UTC
Permalink
Post by Nick Clifton
Hi Andrew,
Post by Andrew Waterman
We'd like to submit for inclusion in Binutils a port for the RISC-V
architecture.
Thanks very much for submitting these patches. Before going any further
though, I have to ask: do all of the authors of these patches have FSF
binutils copyright assignments in place ? I see that SiFive have an
assignment, but are there any other authors involved in this work, and if
so, do they have copyright assignments ?
My understanding is that everyone has the correct copyright assignment
paperwork filed with the FSF, which is what prompted us to finally pull the
trigger on upstreaming.
Post by Nick Clifton
The next question is: is someone volunteering to be a maintainer for this
port ? A port without a maintainer is likely to bit-rot and eventually be
rendered obsolete. On the other hand volunteering to be a maintainer
should not be taken lightly as it does involve a commitment.
Andrew and I will volunteer to be maintainers of the RISC-V toolchain,
including the binutils port.
Post by Nick Clifton
Lastly - are there publicly available documents describing the RISC-V ISA ?
It is handy to be able to refer to these if any questions arise about the
accuracy of the port.
The RISC-V foundation's website has both the user-level ISA spec and a draft of
the privileged spec:

https://riscv.org/specifications/
Nick Clifton
2016-10-17 10:52:26 UTC
Permalink
Hi Palmer,
Post by Palmer Dabbelt
My understanding is that everyone has the correct copyright assignment
paperwork filed with the FSF, which is what prompted us to finally pull the
trigger on upstreaming.
Excellent - thanks very much.
Post by Palmer Dabbelt
Andrew and I will volunteer to be maintainers of the RISC-V toolchain,
including the binutils port.
Yay - welcome to the team!
Post by Palmer Dabbelt
The RISC-V foundation's website has both the user-level ISA spec and a draft of
https://riscv.org/specifications/
Thanks - I have grabbed a copy of the v2.1 spec for later perusal.

Cheers
Nick
Palmer Dabbelt
2016-10-15 19:30:29 UTC
Permalink
Post by Nick Clifton
Hi Andrew,
As an aside I would like to point out that it would be helpful if you
could include proposed ChangeLog entries for each of these patches.
I've been avoiding any ChangeLog stuff because they always cause merge
conflicts. Do you want them included in the patch or in the email that goes
along with the patches?
Post by Nick Clifton
Also with a new target like this, an entry in the gas/NEWS file is
appropriate. Plus I notice that your patch does not add a new
gas/doc/c-riscv.texi file, nor does it update gas/doc/as.texinfo,
and it does not appear to contain a new sub-directory in
gas/testsuite/gas for RISC-V specific tests. All of these would
really be appreciated.
How do these look?

https://github.com/riscv/riscv-binutils-gdb/commit/84fbe7dc2a007898e8b9cbfa865313f979db09e3
https://github.com/riscv/riscv-binutils-gdb/commit/75564972be7916567432daf33b91775e581b646d
https://github.com/riscv/riscv-binutils-gdb/commit/e028448560e2c77d36da572e5ef206e6d9b44873

I have no idea how to format the NEWS entry, sorry.

I know the test case is pretty anemic, but I'm not sure how to run the GAS test
suite. We've just been running GCC tests. There is a RISC-V ISA test suite
that I can copy into the GAS port if you want, but I generally don't like
having copies of stuff floating around.

I'm also not sure how to build or view the texinfo documentation.
Post by Nick Clifton
Post by Andrew Waterman
+/* tc-riscv.c -- RISC-V assembler
+ Copyright 2011-2015 Free Software Foundation, Inc.
Given that this file is only being contributed in 2016, it is difficult
to see how the FSF can claim copyright for 2011..2015. :-) (The same
thing applies to the other new files too...)
Our port was originally based on the MIPS port, but also contains a lot of code
from the Tilera and ARMv8 ports. Since we started by copying a lot of their
files we left the copyright headers intact. If that's not how it's supposed to
work then I can go change all the copyright dates, but my understand is that
these files are actually copyright FSF as of whatever their dates say.
Post by Nick Clifton
Post by Andrew Waterman
+riscv_set_arch (const char *arg)
+{
+ char *uppercase = xstrdup (arg);
+ char *p = uppercase;
+ const char *all_subsets = "IMAFDC";
+ const char *extension = NULL;
+ int rvc = 0;
+ int i;
+
+ for (i = 0; uppercase[i]; i++)
+ uppercase[i] = TOUPPER (uppercase[i]);
You could save code space and memory allocation by using strncasecmp
instead if strncmp...
https://github.com/riscv/riscv-binutils-gdb/commit/232a17acdbff520ea377d25b61d1dc553e9d51a2
Post by Nick Clifton
Post by Andrew Waterman
+/* handle of the OPCODE hash table */
Comment formatting - upper case first letter, period and two spaces at
the end.
https://github.com/riscv/riscv-binutils-gdb/commit/1160cd8d1fb7f6bd84c20a95563c5a583cfaa372
Post by Nick Clifton
Post by Andrew Waterman
+static int
+relaxed_branch_length (fragS *fragp, asection *sec, int update)
Can a relaxed branch ever have a negative length ? If not then "unsigned int"
would be a more appropriate return type.
https://github.com/riscv/riscv-binutils-gdb/commit/361efaa29c26c3c9194898376adf629d0b588a96
Post by Nick Clifton
Post by Andrew Waterman
+static int
+arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
Similarly this appears to be a boolean function so bfd_boolean would be a more
appropriate return type. (Actually there appear to be quite a few functions that
should be returning a boolean).
https://github.com/riscv/riscv-binutils-gdb/commit/6aba295443e4fdfd2fe9c13268addde98b999251
Post by Nick Clifton
Post by Andrew Waterman
+append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
+ bfd_reloc_code_real_type reloc_type)
+{
+#ifdef OBJ_ELF
+ dwarf2_emit_insn (0);
+#endif
Are you supporting file formats other than ELF ? If not, then there
is no need for the conditionals around this code.
https://github.com/riscv/riscv-binutils-gdb/commit/31454d5265bec2733075daf668b6ba70fd6e99ff
Post by Nick Clifton
Post by Andrew Waterman
+ switch (elf_float_mode)
+ {
+ as_bad ("a specific float mode must be specified for an ELF");
+ break;
This error message looks a little wrong to me. I think that
dropping the "for an ELF" part would make more sense.
I think this is actually correct. The idea here is that ELF files in RISC-V
can be tagged with the floating-point ABI. This lets us avoid linking ELFs
with incompatible ABIs, much like 32-bit vs 64-bit ELFs. So in this case I
believe the "for an ELF" is necessary -- without it users might thing there's
something wrong with their GAS command-line arguments.
Post by Nick Clifton
Post by Andrew Waterman
+void
+md_show_usage (FILE *stream)
+{
+ fprintf (stream, _("\
+RISC-V options:\n\
+ -m32 assemble RV32 code\n\
+ -m64 assemble RV64 code (default)\n\
+ -fpic generate position-independent code\n\
+ -fno-pic don't generate position-independent code (default)\n\
+"));
There are more command line options supported than those show here.
-march, -mrvc, -msoft-float and -mhard-float for example.
I think I got them all:

struct option md_longopts[] =
{
{"m32", no_argument, NULL, OPTION_M32},
{"m64", no_argument, NULL, OPTION_M64},
{"march", required_argument, NULL, OPTION_MARCH},
{"fPIC", no_argument, NULL, OPTION_PIC},
{"fpic", no_argument, NULL, OPTION_PIC},
{"fno-pic", no_argument, NULL, OPTION_NO_PIC},
{"mrvc", no_argument, NULL, OPTION_MRVC},
{"mno-rvc", no_argument, NULL, OPTION_MNO_RVC},
{"msoft-float", no_argument, NULL, OPTION_MSOFT_FLOAT},
{"mhard-float", no_argument, NULL, OPTION_MHARD_FLOAT},

{NULL, no_argument, NULL, 0}
};

https://github.com/riscv/riscv-binutils-gdb/commit/f70faf1c3fe6cb2f5980d5c986a58ffcfac612fa
Post by Nick Clifton
Cheers
Nick
Thanks for the comments!
Nick Clifton
2016-10-17 12:09:06 UTC
Permalink
Hi Palmer,
Post by Palmer Dabbelt
Post by Nick Clifton
As an aside I would like to point out that it would be helpful if you
could include proposed ChangeLog entries for each of these patches.
I've been avoiding any ChangeLog stuff because they always cause merge
conflicts. Do you want them included in the patch or in the email that goes
along with the patches?
In the email alongside the patches please. Just as plain text, not a context
diff. As you say the changelogs update so frequently that a changelog in the
patch almost never applies cleanly.
Post by Palmer Dabbelt
Post by Nick Clifton
Also with a new target like this, an entry in the gas/NEWS file is
appropriate. Plus I notice that your patch does not add a new
gas/doc/c-riscv.texi file, nor does it update gas/doc/as.texinfo,
and it does not appear to contain a new sub-directory in
gas/testsuite/gas for RISC-V specific tests. All of these would
really be appreciated.
How do these look?
Very nice.
Post by Palmer Dabbelt
https://github.com/riscv/riscv-binutils-gdb/commit/84fbe7dc2a007898e8b9cbfa865313f979db09e3
https://github.com/riscv/riscv-binutils-gdb/commit/75564972be7916567432daf33b91775e581b646d
https://github.com/riscv/riscv-binutils-gdb/commit/e028448560e2c77d36da572e5ef206e6d9b44873
I have no idea how to format the NEWS entry, sorry.
Just as you did is fine.
Post by Palmer Dabbelt
I know the test case is pretty anemic, but I'm not sure how to run the GAS test
suite.
GAS tests are run in pretty much the same way as GCC tests. You build a toolchain,
go into the gas directory and run "make check".
Post by Palmer Dabbelt
We've just been running GCC tests. There is a RISC-V ISA test suite
that I can copy into the GAS port if you want, but I generally don't like
having copies of stuff floating around.
Do the GCC tests just check the assembler output from the compiler, or do they
also include checking the output of the assembler and disassembler ? If they do
all three things then I agree that the GAS tests would be mostly redundant. But
they do still serve a purpose. Or several really - they can be run without needing
a compiler - they can test the generation of instructions that the compiler will
not generate - they can test assembler features that the compiler does not use.

I will not insist on an assembler testsuite being included as part of the
contribution, but I do think that it is in your interest to have one. Perhaps as a
later update.
Post by Palmer Dabbelt
I'm also not sure how to build or view the texinfo documentation.
Running "make info" in the gas build directory should do the trick. Then running
info ./doc/as.info should allow you to read the documentation. Or running
"nroff -man ./doc/as.1" to check the manual page.
Post by Palmer Dabbelt
Our port was originally based on the MIPS port, but also contains a lot of code
from the Tilera and ARMv8 ports. Since we started by copying a lot of their
files we left the copyright headers intact. If that's not how it's supposed to
work then I can go change all the copyright dates, but my understand is that
these files are actually copyright FSF as of whatever their dates say.
Fair enough - but please could you extend the dates to include 2016, since that
is the year in which the sources will be added to the repository.
Post by Palmer Dabbelt
https://github.com/riscv/riscv-binutils-gdb/commit/31454d5265bec2733075daf668b6ba70fd6e99ff
Post by Nick Clifton
Post by Andrew Waterman
+ switch (elf_float_mode)
+ {
+ as_bad ("a specific float mode must be specified for an ELF");
+ break;
This error message looks a little wrong to me. I think that
dropping the "for an ELF" part would make more sense.
I think this is actually correct. The idea here is that ELF files in RISC-V
can be tagged with the floating-point ABI. This lets us avoid linking ELFs
with incompatible ABIs, much like 32-bit vs 64-bit ELFs. So in this case I
believe the "for an ELF" is necessary -- without it users might thing there's
something wrong with their GAS command-line arguments.
OK, but "ELF" is just a binary file format - ie an abstract thing - and not a
physical object like an actual file. Most users would, at least in my opinion,
refer to binary files as "object files" or "executables" or "libraries", not
"ELFs". So how about this alternative wording:

a specific float mode must be specified for the output file

or even:

a specific float mode must be specified in order for the output file to be valid

or just:

please specify the float mode for the output

Cheers
Nick

PS. I am going to wait for the v2 patches to be posted and then try reviewing
en masse again.
Palmer Dabbelt
2016-10-15 19:30:31 UTC
Permalink
Post by Nick Clifton
Hi Andrew,
Post by Andrew Waterman
+++ b/include/opcode/riscv-opc.h
@@ -0,0 +1,1160 @@
+/* Automatically generated by parse-opcodes */
If this file is generated by a tool, then that tool (and input files it
requires) should be part of the submission too. Either that, or else
these generated files should be changed to be considered to be the
originals, and no generator mentioned or needed.
It's autogenerated by riscv-opcodes

https://github.com/riscv/riscv-opcodes

At least the user-level constants are pretty much set in stone (the privileged
ISA is on 1.9.1, so it could change some, but the user ISA is on 2.1 so it
won't make backwards-incompatible changes).

Should I drop the comment?
Joseph Myers
2016-10-16 13:36:19 UTC
Permalink
Post by Palmer Dabbelt
Post by Nick Clifton
If this file is generated by a tool, then that tool (and input files it
requires) should be part of the submission too. Either that, or else
these generated files should be changed to be considered to be the
originals, and no generator mentioned or needed.
It's autogenerated by riscv-opcodes
https://github.com/riscv/riscv-opcodes
The GPL requires that binutils includes the source code - the preferred
form of the code for making changes to it. Thus, if the preferred form of
the code for making changes to that file is in riscv-opcodes, the relevant
riscv-opcodes code must be included in the binutils sources. This is just
like various CGEN input files are included in the binutils sources (and
some past release tarballs had to be recreated a while back when it was
found they were missing some such input files and so not legally
distributable).
--
Joseph S. Myers
***@codesourcery.com
Palmer Dabbelt
2016-10-15 19:30:32 UTC
Permalink
Post by Nick Clifton
Hi Andrew,
Post by Andrew Waterman
We'd like to submit for inclusion in Binutils a port for the RISC-V
architecture.
One other thing that I forgot to mention. It would be helpful if you
could add a patch to binutils/readelf.c to add code for this target.
guess_is_rela
get_machine_name
is_32bit_abs_reloc
is_32bit_pcrel_reloc
is_none_reloc
Hmm, also I see that you are using an EM_RISCV ELF machine number, but
there does not appear to be a patch to include/elf/common.h to add this
value. Did I miss something ?
I think I screwed something up when splitting the patches for email, because
it's on my "riscv-master" branch (which contains all our commits merged into
binutils-gdb's master branch), but not on my "riscv-for-upstream" branch (which
has all the patches for a directory merged together).

I see EM_RISCV in all the implementations of those functions:

https://github.com/riscv/riscv-binutils-gdb/blob/riscv-master/binutils/readelf.c

Good catch! We're missing a sizeable chunk of the port :). I'm going to
submit a v2 with your suggestions (and everyone else who has commented). I'll
try and screw it up less next time!
Palmer Dabbelt
2016-10-19 17:13:42 UTC
Permalink
Post by Joseph Myers
Post by Palmer Dabbelt
Post by Nick Clifton
If this file is generated by a tool, then that tool (and input files it
requires) should be part of the submission too. Either that, or else
these generated files should be changed to be considered to be the
originals, and no generator mentioned or needed.
It's autogenerated by riscv-opcodes
https://github.com/riscv/riscv-opcodes
The GPL requires that binutils includes the source code - the preferred
form of the code for making changes to it. Thus, if the preferred form of
the code for making changes to that file is in riscv-opcodes, the relevant
riscv-opcodes code must be included in the binutils sources. This is just
like various CGEN input files are included in the binutils sources (and
some past release tarballs had to be recreated a while back when it was
found they were missing some such input files and so not legally
distributable).
OK, sorry -- I guess I'm never really sure about how licenses work. Andrew and
I will either write a new riscv-opc.h by hand (probably based on the ARMv8 one,
as that looks like the newest and cleanest) or clean up and commit the scripts
to generate the header.
Palmer Dabbelt
2016-10-19 18:43:30 UTC
Permalink
Post by Nick Clifton
Hi Palmer,
Post by Palmer Dabbelt
My understanding is that everyone has the correct copyright assignment
paperwork filed with the FSF, which is what prompted us to finally pull the
trigger on upstreaming.
Excellent - thanks very much.
Post by Palmer Dabbelt
Andrew and I will volunteer to be maintainers of the RISC-V toolchain,
including the binutils port.
Yay - welcome to the team!
Post by Palmer Dabbelt
The RISC-V foundation's website has both the user-level ISA spec and a draft of
https://riscv.org/specifications/
Thanks - I have grabbed a copy of the v2.1 spec for later perusal.
If you have any questions, the RISC-V mailing lists are a good place to go:

https://riscv.org/mailing-lists/
Palmer Dabbelt
2016-10-19 18:43:31 UTC
Permalink
Post by Nick Clifton
Post by Palmer Dabbelt
We've just been running GCC tests. There is a RISC-V ISA test suite
that I can copy into the GAS port if you want, but I generally don't like
having copies of stuff floating around.
Do the GCC tests just check the assembler output from the compiler, or do they
also include checking the output of the assembler and disassembler ? If they do
all three things then I agree that the GAS tests would be mostly redundant. But
they do still serve a purpose. Or several really - they can be run without needing
a compiler - they can test the generation of instructions that the compiler will
not generate - they can test assembler features that the compiler does not use.
I will not insist on an assembler testsuite being included as part of the
contribution, but I do think that it is in your interest to have one. Perhaps as a
later update.
As far as I know, the GCC test suite won't do a good job testing disassembly.
I think I'm going to hold off on committing a larger test suite until later.
Doing a good job here is going to be a lot of work, and I think doing a bad job
won't get us anything.
Post by Nick Clifton
Post by Palmer Dabbelt
Our port was originally based on the MIPS port, but also contains a lot of code
from the Tilera and ARMv8 ports. Since we started by copying a lot of their
files we left the copyright headers intact. If that's not how it's supposed to
work then I can go change all the copyright dates, but my understand is that
these files are actually copyright FSF as of whatever their dates say.
Fair enough - but please could you extend the dates to include 2016, since that
is the year in which the sources will be added to the repository.
If there were any copyrights that don't include 2016 then I just missed them.
That's likely, as I miss these a lot.
Post by Nick Clifton
Post by Palmer Dabbelt
https://github.com/riscv/riscv-binutils-gdb/commit/31454d5265bec2733075daf668b6ba70fd6e99ff
Post by Nick Clifton
Post by Andrew Waterman
+ switch (elf_float_mode)
+ {
+ as_bad ("a specific float mode must be specified for an ELF");
+ break;
This error message looks a little wrong to me. I think that
dropping the "for an ELF" part would make more sense.
I think this is actually correct. The idea here is that ELF files in RISC-V
can be tagged with the floating-point ABI. This lets us avoid linking ELFs
with incompatible ABIs, much like 32-bit vs 64-bit ELFs. So in this case I
believe the "for an ELF" is necessary -- without it users might thing there's
something wrong with their GAS command-line arguments.
OK, but "ELF" is just a binary file format - ie an abstract thing - and not a
physical object like an actual file. Most users would, at least in my opinion,
refer to binary files as "object files" or "executables" or "libraries", not
a specific float mode must be specified for the output file
a specific float mode must be specified in order for the output file to be valid
please specify the float mode for the output
Good news: this error handling code has been removed and is replaced with a
more robust way to pass around the floating point ABIs.
Post by Nick Clifton
PS. I am going to wait for the v2 patches to be posted and then try reviewing
en masse again.
Thanks! I'll try and get out a v2 today.

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